forked from OSchip/llvm-project
[mips][ias] Check '$rs = $rd' constraints when both registers are in AsmText.
Summary: This is one possible solution to the problem of ignoring constraints that Simon raised in D21473 but it's a bit of a hack. The integrated assembler currently ignores violations of the tied register constraints when the operands involved in a tie are both present in the AsmText. For example, 'dati $rs, $rt, $imm' with the '$rs = $rt' will silently replace $rt with $rs. So 'dati $2, $3, 1' is processed as if the user provided 'dati $2, $2, 1' without any diagnostic being emitted. This is difficult to solve properly because there are multiple parts of the matcher that are silently forcing these constraints to be met. Tied operands are rendered to instructions by cloning previously rendered operands but this is unnecessary because the matcher was already instructed to render the operand it would have cloned. This is also unnecessary because earlier code has already replaced the MCParsedOperand with the one it was tied to (so the parsed input is matched as if it were 'dati <RegIdx 2>, <RegIdx 2>, <Imm 1>'). As a result, it looks like fixing this properly amounts to a rewrite of the tied operand handling which affects all targets. This patch however, merely inserts a checking hook just before the substitution of MCParsedOperands and the Mips target overrides it. It's not possible to accurately check the registers are the same this early (because numeric registers haven't been bound to a register class yet) so it cheats a bit and checks that the tokens that produced the operand are lexically identical. This works because tied registers need to have the same register class but it does have a flaw. It will reject 'dati $4, $a0, 1' for violating the constraint even though $a0 ends up as the same register as $4. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: https://reviews.llvm.org/D21994 llvm-svn: 276867
This commit is contained in:
Daniel Sanders
parent
5b7f016f41
commit
c5537427c2
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@ -196,6 +196,13 @@ public:
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return Match_InvalidOperand;
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}
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/// Validate the instruction match against any complex target predicates
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/// before rendering any operands to it.
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virtual unsigned
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checkEarlyTargetMatchPredicate(MCInst &Inst, const OperandVector &Operands) {
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return Match_Success;
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}
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/// checkTargetMatchPredicate - Validate the instruction match against
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/// any complex target predicates not expressible via match classes.
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virtual unsigned checkTargetMatchPredicate(MCInst &Inst) {
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@ -129,6 +129,9 @@ class MipsAsmParser : public MCTargetAsmParser {
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#define GET_ASSEMBLER_HEADER
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#include "MipsGenAsmMatcher.inc"
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unsigned
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checkEarlyTargetMatchPredicate(MCInst &Inst,
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const OperandVector &Operands) override;
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unsigned checkTargetMatchPredicate(MCInst &Inst) override;
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bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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@ -395,6 +398,7 @@ public:
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Match_RequiresDifferentSrcAndDst = FIRST_TARGET_MATCH_RESULT_TY,
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Match_RequiresDifferentOperands,
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Match_RequiresNoZeroRegister,
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Match_RequiresSameSrcAndDst,
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#define GET_OPERAND_DIAGNOSTIC_TYPES
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#include "MipsGenAsmMatcher.inc"
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#undef GET_OPERAND_DIAGNOSTIC_TYPES
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@ -605,6 +609,7 @@ private:
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struct RegIdxOp {
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unsigned Index; /// Index into the register class
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RegKind Kind; /// Bitfield of the kinds it could possibly be
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struct Token Tok; /// The input token this operand originated from.
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const MCRegisterInfo *RegInfo;
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};
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@ -632,7 +637,8 @@ private:
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SMLoc StartLoc, EndLoc;
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/// Internal constructor for register kinds
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static std::unique_ptr<MipsOperand> CreateReg(unsigned Index, RegKind RegKind,
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static std::unique_ptr<MipsOperand> CreateReg(unsigned Index, StringRef Str,
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RegKind RegKind,
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const MCRegisterInfo *RegInfo,
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SMLoc S, SMLoc E,
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MipsAsmParser &Parser) {
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@ -640,6 +646,8 @@ private:
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Op->RegIdx.Index = Index;
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Op->RegIdx.RegInfo = RegInfo;
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Op->RegIdx.Kind = RegKind;
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Op->RegIdx.Tok.Data = Str.data();
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Op->RegIdx.Tok.Length = Str.size();
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Op->StartLoc = S;
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Op->EndLoc = E;
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return Op;
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@ -1228,66 +1236,66 @@ public:
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/// Create a numeric register (e.g. $1). The exact register remains
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/// unresolved until an instruction successfully matches
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static std::unique_ptr<MipsOperand>
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createNumericReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S,
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SMLoc E, MipsAsmParser &Parser) {
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createNumericReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
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SMLoc S, SMLoc E, MipsAsmParser &Parser) {
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DEBUG(dbgs() << "createNumericReg(" << Index << ", ...)\n");
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return CreateReg(Index, RegKind_Numeric, RegInfo, S, E, Parser);
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return CreateReg(Index, Str, RegKind_Numeric, RegInfo, S, E, Parser);
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}
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/// Create a register that is definitely a GPR.
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/// This is typically only used for named registers such as $gp.
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static std::unique_ptr<MipsOperand>
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createGPRReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
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MipsAsmParser &Parser) {
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return CreateReg(Index, RegKind_GPR, RegInfo, S, E, Parser);
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createGPRReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
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SMLoc S, SMLoc E, MipsAsmParser &Parser) {
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return CreateReg(Index, Str, RegKind_GPR, RegInfo, S, E, Parser);
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}
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/// Create a register that is definitely a FGR.
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/// This is typically only used for named registers such as $f0.
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static std::unique_ptr<MipsOperand>
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createFGRReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
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MipsAsmParser &Parser) {
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return CreateReg(Index, RegKind_FGR, RegInfo, S, E, Parser);
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createFGRReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
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SMLoc S, SMLoc E, MipsAsmParser &Parser) {
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return CreateReg(Index, Str, RegKind_FGR, RegInfo, S, E, Parser);
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}
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/// Create a register that is definitely a HWReg.
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/// This is typically only used for named registers such as $hwr_cpunum.
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static std::unique_ptr<MipsOperand>
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createHWRegsReg(unsigned Index, const MCRegisterInfo *RegInfo,
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createHWRegsReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
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SMLoc S, SMLoc E, MipsAsmParser &Parser) {
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return CreateReg(Index, RegKind_HWRegs, RegInfo, S, E, Parser);
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return CreateReg(Index, Str, RegKind_HWRegs, RegInfo, S, E, Parser);
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}
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/// Create a register that is definitely an FCC.
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/// This is typically only used for named registers such as $fcc0.
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static std::unique_ptr<MipsOperand>
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createFCCReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
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MipsAsmParser &Parser) {
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return CreateReg(Index, RegKind_FCC, RegInfo, S, E, Parser);
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createFCCReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
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SMLoc S, SMLoc E, MipsAsmParser &Parser) {
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return CreateReg(Index, Str, RegKind_FCC, RegInfo, S, E, Parser);
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}
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/// Create a register that is definitely an ACC.
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/// This is typically only used for named registers such as $ac0.
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static std::unique_ptr<MipsOperand>
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createACCReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
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MipsAsmParser &Parser) {
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return CreateReg(Index, RegKind_ACC, RegInfo, S, E, Parser);
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createACCReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
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SMLoc S, SMLoc E, MipsAsmParser &Parser) {
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return CreateReg(Index, Str, RegKind_ACC, RegInfo, S, E, Parser);
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}
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/// Create a register that is definitely an MSA128.
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/// This is typically only used for named registers such as $w0.
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static std::unique_ptr<MipsOperand>
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createMSA128Reg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S,
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SMLoc E, MipsAsmParser &Parser) {
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return CreateReg(Index, RegKind_MSA128, RegInfo, S, E, Parser);
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createMSA128Reg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
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SMLoc S, SMLoc E, MipsAsmParser &Parser) {
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return CreateReg(Index, Str, RegKind_MSA128, RegInfo, S, E, Parser);
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}
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/// Create a register that is definitely an MSACtrl.
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/// This is typically only used for named registers such as $msaaccess.
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static std::unique_ptr<MipsOperand>
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createMSACtrlReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S,
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SMLoc E, MipsAsmParser &Parser) {
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return CreateReg(Index, RegKind_MSACtrl, RegInfo, S, E, Parser);
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createMSACtrlReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
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SMLoc S, SMLoc E, MipsAsmParser &Parser) {
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return CreateReg(Index, Str, RegKind_MSACtrl, RegInfo, S, E, Parser);
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}
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static std::unique_ptr<MipsOperand>
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@ -1428,10 +1436,11 @@ public:
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OS << ">";
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break;
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case k_RegisterIndex:
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OS << "RegIdx<" << RegIdx.Index << ":" << RegIdx.Kind << ">";
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OS << "RegIdx<" << RegIdx.Index << ":" << RegIdx.Kind << ", "
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<< StringRef(RegIdx.Tok.Data, RegIdx.Tok.Length) << ">";
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break;
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case k_Token:
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OS << Tok.Data;
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OS << getToken();
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break;
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case k_RegList:
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OS << "RegList< ";
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@ -1444,6 +1453,22 @@ public:
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break;
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}
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}
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bool isValidForTie(const MipsOperand &Other) const {
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if (Kind != Other.Kind)
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return false;
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switch (Kind) {
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default:
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llvm_unreachable("Unexpected kind");
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return false;
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case k_RegisterIndex: {
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StringRef Token(RegIdx.Tok.Data, RegIdx.Tok.Length);
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StringRef OtherToken(Other.RegIdx.Tok.Data, Other.RegIdx.Tok.Length);
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return Token == OtherToken;
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}
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}
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}
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}; // class MipsOperand
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} // namespace
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@ -3685,6 +3710,20 @@ bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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return false;
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}
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unsigned
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MipsAsmParser::checkEarlyTargetMatchPredicate(MCInst &Inst,
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const OperandVector &Operands) {
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switch (Inst.getOpcode()) {
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default:
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return Match_Success;
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case Mips::DATI:
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case Mips::DAHI:
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return static_cast<MipsOperand &>(*Operands[1])
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.isValidForTie(static_cast<MipsOperand &>(*Operands[2]))
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? Match_Success
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: Match_RequiresSameSrcAndDst;
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}
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}
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unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
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switch (Inst.getOpcode()) {
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// As described by the Mips32r2 spec, the registers Rd and Rs for
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@ -3807,6 +3846,8 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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return Error(IDLoc, "registers must be different");
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case Match_RequiresNoZeroRegister:
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return Error(IDLoc, "invalid operand ($zero) for instruction");
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case Match_RequiresSameSrcAndDst:
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return Error(IDLoc, "source and destination must match");
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case Match_Immz:
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return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected '0'");
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case Match_UImm1_0:
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@ -4398,8 +4439,8 @@ MipsAsmParser::parseMemOperand(OperandVector &Operands) {
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// Zero register assumed, add a memory operand with ZERO as its base.
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// "Base" will be managed by k_Memory.
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auto Base = MipsOperand::createGPRReg(0, getContext().getRegisterInfo(),
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S, E, *this);
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auto Base = MipsOperand::createGPRReg(
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0, "0", getContext().getRegisterInfo(), S, E, *this);
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Operands.push_back(
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MipsOperand::CreateMem(std::move(Base), IdVal, S, E, *this));
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return MatchOperand_Success;
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@ -4482,49 +4523,56 @@ MipsAsmParser::matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
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int Index = matchCPURegisterName(Identifier);
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if (Index != -1) {
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Operands.push_back(MipsOperand::createGPRReg(
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Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
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Index, Identifier, getContext().getRegisterInfo(), S,
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getLexer().getLoc(), *this));
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return MatchOperand_Success;
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}
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Index = matchHWRegsRegisterName(Identifier);
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if (Index != -1) {
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Operands.push_back(MipsOperand::createHWRegsReg(
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Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
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Index, Identifier, getContext().getRegisterInfo(), S,
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getLexer().getLoc(), *this));
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return MatchOperand_Success;
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}
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Index = matchFPURegisterName(Identifier);
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if (Index != -1) {
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Operands.push_back(MipsOperand::createFGRReg(
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Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
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Index, Identifier, getContext().getRegisterInfo(), S,
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getLexer().getLoc(), *this));
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return MatchOperand_Success;
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}
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Index = matchFCCRegisterName(Identifier);
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if (Index != -1) {
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Operands.push_back(MipsOperand::createFCCReg(
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Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
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Index, Identifier, getContext().getRegisterInfo(), S,
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getLexer().getLoc(), *this));
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return MatchOperand_Success;
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}
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Index = matchACRegisterName(Identifier);
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if (Index != -1) {
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Operands.push_back(MipsOperand::createACCReg(
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Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
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Index, Identifier, getContext().getRegisterInfo(), S,
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getLexer().getLoc(), *this));
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return MatchOperand_Success;
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}
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Index = matchMSA128RegisterName(Identifier);
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if (Index != -1) {
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Operands.push_back(MipsOperand::createMSA128Reg(
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Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
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Index, Identifier, getContext().getRegisterInfo(), S,
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getLexer().getLoc(), *this));
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return MatchOperand_Success;
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}
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Index = matchMSA128CtrlRegisterName(Identifier);
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if (Index != -1) {
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Operands.push_back(MipsOperand::createMSACtrlReg(
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Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
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Index, Identifier, getContext().getRegisterInfo(), S,
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getLexer().getLoc(), *this));
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return MatchOperand_Success;
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}
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@ -4545,8 +4593,8 @@ MipsAsmParser::matchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S) {
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} else if (Token.is(AsmToken::Integer)) {
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DEBUG(dbgs() << ".. integer\n");
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Operands.push_back(MipsOperand::createNumericReg(
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Token.getIntVal(), getContext().getRegisterInfo(), S, Token.getLoc(),
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*this));
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Token.getIntVal(), Token.getString(), getContext().getRegisterInfo(), S,
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Token.getLoc(), *this));
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return MatchOperand_Success;
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}
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@ -49,7 +49,7 @@ class SCD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SCD>;
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class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, InstrItinClass itin> {
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dag OutOperandList = (outs GPROpnd:$rs);
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dag InOperandList = (ins GPROpnd:$rt, simm16_relaxed:$imm);
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string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
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string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
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string Constraints = "$rs = $rt";
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InstrItinClass Itinerary = itin;
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}
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@ -94,7 +94,7 @@
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0x85 0x18 0x84 0x46 # CHECK: cmp.ult.s $f2, $f3, $f4
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0x81 0x18 0xa4 0x46 # CHECK: cmp.un.d $f2, $f3, $f4
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0x81 0x18 0x84 0x46 # CHECK: cmp.un.s $f2, $f3, $f4
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0x78 0x56 0x66 0x04 # CHECK: dahi $3, 22136
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0x78 0x56 0x66 0x04 # CHECK: dahi $3, $3, 22136
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0x64 0x23 0x43 0x7c # CHECK: dalign $4, $2, $3, 5
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0x34 0x12 0x62 0x74 # CHECK: daui $3, $2, 4660
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0x24 0x20 0x02 0x7c # CHECK: dbitswap $4, $2
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@ -50,8 +50,8 @@
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0x03 0xe0 0x78 0x25 # CHECK: move $15, $ra
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0x03 0xe0 0x78 0x2d # CHECK: move $15, $ra
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0x04 0x11 0x14 0x9b # CHECK: bal 21104
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0x04 0x66 0x56 0x78 # CHECK: dahi $3, 22136
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0x04 0x7e 0xab 0xcd # CHECK: dati $3, -21555
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0x04 0x66 0x56 0x78 # CHECK: dahi $3, $3, 22136
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0x04 0x7e 0xab 0xcd # CHECK: dati $3, $3, -21555
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# The encode/decode functions are not inverses of each other in the immediate case.
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0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1336
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0x18 0x02 0xff 0xfa # CHECk: blezalc $2, -20
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@ -20,6 +20,7 @@ local_label:
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break 7, -1 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate
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break 7, 1024 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate
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break 1024, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
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dati $2, $3, 1 # CHECK: :[[@LINE]]:9: error: source and destination must match
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lh $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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lhe $34, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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@ -101,12 +101,12 @@ a:
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cmp.ult.s $f2,$f3,$f4 # CHECK: cmp.ult.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x85]
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cmp.un.d $f2,$f3,$f4 # CHECK: cmp.un.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x81]
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cmp.un.s $f2,$f3,$f4 # CHECK: cmp.un.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x81]
|
||||
daddu $19,26943 # CHECK: daddiu $19, $19, 26943 # encoding: [0x66,0x73,0x69,0x3f]
|
||||
daddu $24,$2,18079 # CHECK: daddiu $24, $2, 18079 # encoding: [0x64,0x58,0x46,0x9f]
|
||||
dahi $3,0x5678 # CHECK: dahi $3, 22136 # encoding: [0x04,0x66,0x56,0x78]
|
||||
dalign $4,$2,$3,5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x7c,0x43,0x23,0x64]
|
||||
dati $3,0xabcd # CHECK: dati $3, -21555 # encoding: [0x04,0x7e,0xab,0xcd]
|
||||
daui $3,$2,0x1234 # CHECK: daui $3, $2, 4660 # encoding: [0x74,0x62,0x12,0x34]
|
||||
daddu $19,26943 # CHECK: daddiu $19, $19, 26943 # encoding: [0x66,0x73,0x69,0x3f]
|
||||
daddu $24,$2,18079 # CHECK: daddiu $24, $2, 18079 # encoding: [0x64,0x58,0x46,0x9f]
|
||||
dahi $3,$3,0x5678 # CHECK: dahi $3, $3, 22136 # encoding: [0x04,0x66,0x56,0x78]
|
||||
dalign $4,$2,$3,5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x7c,0x43,0x23,0x64]
|
||||
dati $3,$3,0xabcd # CHECK: dati $3, $3, -21555 # encoding: [0x04,0x7e,0xab,0xcd]
|
||||
daui $3,$2,0x1234 # CHECK: daui $3, $2, 4660 # encoding: [0x74,0x62,0x12,0x34]
|
||||
dbitswap $4, $2 # CHECK: dbitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x24]
|
||||
dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x00,0xc0,0x90,0x53]
|
||||
dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x03,0x20,0x80,0x52]
|
||||
|
|
|
|||
|
|
@ -3254,8 +3254,24 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
|
|||
OS << " }\n";
|
||||
OS << "\n";
|
||||
OS << " Inst.clear();\n\n";
|
||||
OS << " Inst.setOpcode(it->Opcode);\n";
|
||||
// Verify the instruction with the target-specific match predicate function.
|
||||
OS << " // We have a potential match but have not rendered the operands.\n"
|
||||
<< " // Check the target predicate to handle any context sensitive\n"
|
||||
" // constraints.\n"
|
||||
<< " // For example, Ties that are referenced multiple times must be\n"
|
||||
" // checked here to ensure the input is the same for each match\n"
|
||||
" // constraints. If we leave it any later the ties will have been\n"
|
||||
" // canonicalized\n"
|
||||
<< " unsigned MatchResult;\n"
|
||||
<< " if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, "
|
||||
"Operands)) != Match_Success) {\n"
|
||||
<< " Inst.clear();\n"
|
||||
<< " RetCode = MatchResult;\n"
|
||||
<< " HadMatchOtherThanPredicate = true;\n"
|
||||
<< " continue;\n"
|
||||
<< " }\n\n";
|
||||
OS << " if (matchingInlineAsm) {\n";
|
||||
OS << " Inst.setOpcode(it->Opcode);\n";
|
||||
OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n";
|
||||
OS << " return Match_Success;\n";
|
||||
OS << " }\n\n";
|
||||
|
|
@ -3272,7 +3288,6 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
|
|||
// Verify the instruction with the target-specific match predicate function.
|
||||
OS << " // We have a potential match. Check the target predicate to\n"
|
||||
<< " // handle any context sensitive constraints.\n"
|
||||
<< " unsigned MatchResult;\n"
|
||||
<< " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
|
||||
<< " Match_Success) {\n"
|
||||
<< " Inst.clear();\n"
|
||||
|
|
|
|||
Loading…
Reference in New Issue