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[RISCV] Split f64 undef into two i32 undefs 

So that no store instruction will be generated.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D118222
This commit is contained in:
wangpc 2022-02-08 13:42:15 +08:00
parent adbc7a2665
commit c53d99c37d
2 changed files with 6 additions and 5 deletions
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6
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View File

@ -7796,6 +7796,12 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
if (Op0->getOpcode() == RISCVISD::BuildPairF64)
return DCI.CombineTo(N, Op0.getOperand(0), Op0.getOperand(1));
if (Op0->isUndef()) {
SDValue Lo = DAG.getUNDEF(MVT::i32);
SDValue Hi = DAG.getUNDEF(MVT::i32);
return DCI.CombineTo(N, Lo, Hi);
}
SDLoc DL(N);
// It's cheaper to materialise two 32-bit integers than to load a double

5
llvm/test/CodeGen/RISCV/double-calling-conv.ll
View File

@ -146,11 +146,6 @@ define double @caller_double_stack() nounwind {
define double @func_return_double_undef() nounwind {
; RV32IFD-LABEL: func_return_double_undef:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
ret double undef
}