diff --git a/clang/lib/Basic/Targets/Hexagon.cpp b/clang/lib/Basic/Targets/Hexagon.cpp
index ba10459e9690..d1613fb22930 100644
--- a/clang/lib/Basic/Targets/Hexagon.cpp
+++ b/clang/lib/Basic/Targets/Hexagon.cpp
@@ -136,7 +136,7 @@ const char *const HexagonTargetInfo::GCCRegNames[] = {
     "r9",  "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17",
     "r18", "r19", "r20", "r21", "r22", "r23", "r24", "r25", "r26",
     "r27", "r28", "r29", "r30", "r31", "p0",  "p1",  "p2",  "p3",
-    "sa0", "lc0", "sa1", "lc1", "m0",  "m1",  "usr", "ugp",
+    "sa0", "lc0", "sa1", "lc1", "m0",  "m1",  "usr", "ugp", "cs0", "cs1",
     "r1:0", "r3:2", "r5:4", "r7:6", "r9:8", "r11:10", "r13:12", "r15:14",
     "r17:16", "r19:18", "r21:20", "r23:22", "r25:24", "r27:26", "r29:28",
     "r31:30"
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 30c3d3d4f570..a7e9ed34bfcb 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -308,6 +308,8 @@ Register HexagonTargetLowering::getRegisterByName(
                      .Case("m1", Hexagon::M1)
                      .Case("usr", Hexagon::USR)
                      .Case("ugp", Hexagon::UGP)
+                     .Case("cs0", Hexagon::CS0)
+                     .Case("cs1", Hexagon::CS1)
                      .Default(Register());
   if (Reg)
     return Reg;
diff --git a/llvm/test/CodeGen/Hexagon/namedreg.ll b/llvm/test/CodeGen/Hexagon/namedreg.ll
index 72ca50868828..a905332b2dee 100644
--- a/llvm/test/CodeGen/Hexagon/namedreg.ll
+++ b/llvm/test/CodeGen/Hexagon/namedreg.ll
@@ -4,10 +4,29 @@ entry:
   %0 = call i32 @llvm.read_register.i32(metadata !0)
   ret i32 %0
 }
-
 declare i32 @llvm.read_register.i32(metadata) #1
 
+define dso_local i32 @rcs0() #0 {
+entry:
+  %0 = call i32 @llvm.read_register.i32(metadata !1)
+  ret i32 %0
+}
+
+define dso_local i32 @rcs1() #0 {
+entry:
+  %0 = call i32 @llvm.read_register.i32(metadata !2)
+  ret i32 %0
+}
+
+
+
 !llvm.named.register.r19 = !{!0}
+!llvm.named.register.cs0 = !{!1}
+!llvm.named.register.cs1 = !{!2}
 
 !0 = !{!"r19"}
+!1 = !{!"cs0"}
+!2 = !{!"cs1"}
 ; CHECK: r0 = r19
+; CHECK: r0 = cs0
+; CHECK: r0 = cs1