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[Hexagon] Add support for named registers cs0 and cs1 

Allow inline assembly code to referece cs0 and cs1.
This commit is contained in:
Sid Manning 2021-03-11 11:44:57 -06:00
parent 6333ee2184
commit c539be1dcb
3 changed files with 23 additions and 2 deletions
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2
clang/lib/Basic/Targets/Hexagon.cpp
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@ -136,7 +136,7 @@ const char *const HexagonTargetInfo::GCCRegNames[] = {
"r9", "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17",
"r18", "r19", "r20", "r21", "r22", "r23", "r24", "r25", "r26",
"r27", "r28", "r29", "r30", "r31", "p0", "p1", "p2", "p3",
"sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp",
"sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp", "cs0", "cs1",
"r1:0", "r3:2", "r5:4", "r7:6", "r9:8", "r11:10", "r13:12", "r15:14",
"r17:16", "r19:18", "r21:20", "r23:22", "r25:24", "r27:26", "r29:28",
"r31:30"

2
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -308,6 +308,8 @@ Register HexagonTargetLowering::getRegisterByName(
.Case("m1", Hexagon::M1)
.Case("usr", Hexagon::USR)
.Case("ugp", Hexagon::UGP)
.Case("cs0", Hexagon::CS0)
.Case("cs1", Hexagon::CS1)
.Default(Register());
if (Reg)
return Reg;

21
llvm/test/CodeGen/Hexagon/namedreg.ll
View File

@ -4,10 +4,29 @@ entry:
%0 = call i32 @llvm.read_register.i32(metadata !0)
ret i32 %0
}
declare i32 @llvm.read_register.i32(metadata) #1
define dso_local i32 @rcs0() #0 {
entry:
%0 = call i32 @llvm.read_register.i32(metadata !1)
ret i32 %0
}
define dso_local i32 @rcs1() #0 {
entry:
%0 = call i32 @llvm.read_register.i32(metadata !2)
ret i32 %0
}
!llvm.named.register.r19 = !{!0}
!llvm.named.register.cs0 = !{!1}
!llvm.named.register.cs1 = !{!2}
!0 = !{!"r19"}
!1 = !{!"cs0"}
!2 = !{!"cs1"}
; CHECK: r0 = r19
; CHECK: r0 = cs0
; CHECK: r0 = cs1