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R600/SI: Add soffset operand to mubuf addr64 instruction 

We were previously hard-coding soffset to 0.

llvm-svn: 228775
This commit is contained in:
Tom Stellard 2015-02-11 00:34:32 +00:00
parent f07ef229d3
commit c53861ab84
5 changed files with 33 additions and 28 deletions
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15
llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
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@ -95,9 +95,9 @@ private:
SDValue &Idxen, SDValue &Addr64, SDValue &GLC, SDValue &SLC,
SDValue &TFE) const;
bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
SDValue &Offset) const;
SDValue &SOffset, SDValue &Offset) const;
bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
SDValue &VAddr, SDValue &Offset,
SDValue &VAddr, SDValue &SOffset, SDValue &Offset,
SDValue &SLC) const;
bool SelectMUBUFScratch(SDValue Addr, SDValue &RSrc, SDValue &VAddr,
SDValue &SOffset, SDValue &ImmOffset) const;
@ -964,9 +964,9 @@ void AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr,
}
bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
SDValue &VAddr,
SDValue &VAddr, SDValue &SOffset,
SDValue &Offset) const {
SDValue Ptr, SOffset, Offen, Idxen, Addr64, GLC, SLC, TFE;
SDValue Ptr, Offen, Idxen, Addr64, GLC, SLC, TFE;
SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
GLC, SLC, TFE);
@ -986,11 +986,12 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
}
bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
SDValue &VAddr, SDValue &Offset,
SDValue &SLC) const {
SDValue &VAddr, SDValue &SOffset,
SDValue &Offset,
SDValue &SLC) const {
SLC = CurDAG->getTargetConstant(0, MVT::i1);
return SelectMUBUFAddr64(Addr, SRsrc, VAddr, Offset);
return SelectMUBUFAddr64(Addr, SRsrc, VAddr, SOffset, Offset);
}
bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc,

1
llvm/lib/Target/R600/SIISelLowering.cpp
View File

@ -2124,6 +2124,7 @@ MachineSDNode *SITargetLowering::AdjustRegClass(MachineSDNode *N,
SmallVector<SDValue, 8> Ops;
Ops.push_back(SDValue(RSrc, 0));
Ops.push_back(N->getOperand(0));
Ops.push_back(DAG.getTargetConstant(0, MVT::i32)); // soffset
// The immediate offset is in dwords on SI and in bytes on VI.
if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)

5
llvm/lib/Target/R600/SIInstrInfo.cpp
View File

@ -1729,9 +1729,6 @@ void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata);
MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset);
MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset);
assert(SOffset->isImm() && SOffset->getImm() == 0 && "Legalizing MUBUF "
"with non-zero soffset is not implemented");
(void)SOffset;
// Create the new instruction.
unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode());
@ -1742,6 +1739,7 @@ void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
.addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
// This will be replaced later
// with the new value of vaddr.
.addOperand(*SOffset)
.addOperand(*Offset);
MI->removeFromParent();
@ -1920,6 +1918,7 @@ void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) con
MI->getOperand(2).ChangeToRegister(MI->getOperand(1).getReg(), false);
}
MI->getOperand(1).setReg(SRsrc);
MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0));
MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
const TargetRegisterClass *NewDstRC =

36
llvm/lib/Target/R600/SIInstrInfo.td
View File

@ -292,8 +292,8 @@ def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
def MUBUFAddr64Atomic : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
def MUBUFAddr64 : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
@ -1743,7 +1743,7 @@ multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
AtomicNoRet<NAME#"_ADDR64", is_return>;
let offen = 0, idxen = 0, addr64 = 1, tfe = 0, soffset = 128 in {
let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
}
@ -1781,11 +1781,11 @@ multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
op, name#"_rtn_addr64", (outs rc:$vdata),
(ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
mbuf_offset:$offset, slc:$slc),
name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#" glc"#"$slc",
mbuf_offset:$offset, SSrc_32:$soffset, slc:$slc),
name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
[(set vt:$vdata,
(atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i16:$offset,
i1:$slc), vt:$vdata_in))], 1
(atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
i16:$offset, i1:$slc), vt:$vdata_in))], 1
>;
defm _RTN_OFFSET : MUBUFAtomicOffset_m <
@ -1842,12 +1842,14 @@ multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
name#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
}
let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0 in {
defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
(ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
(ins SReg_128:$srsrc, VReg_64:$vaddr,
SCSrc_32:$soffset, mbuf_offset:$offset),
name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset",
[(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
i64:$vaddr, i16:$offset)))]>;
i64:$vaddr, i32:$soffset,
i16:$offset)))]>;
}
}
}
@ -1879,13 +1881,15 @@ multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
"$glc"#"$slc"#"$tfe", []>;
} // end offen = 1, idxen = 0
let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0,
soffset = 128 /* ZERO */ in {
let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0 in {
defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
(ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
(ins vdataClass:$vdata, SReg_128:$srsrc,
VReg_64:$vaddr, SCSrc_32:$soffset,
mbuf_offset:$offset),
name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset",
[(st store_vt:$vdata,
(MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]>;
(MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
i32:$soffset, i16:$offset))]>;
}
} // End mayLoad = 0, mayStore = 1
}

4
llvm/lib/Target/R600/SIInstructions.td
View File

@ -2877,8 +2877,8 @@ def : DSAtomicCmpXChg<DS_CMPST_RTN_B64, i64, atomic_cmp_swap_64_local>;
multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt,
PatFrag constant_ld> {
def : Pat <
(vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))),
(Instr_ADDR64 $srsrc, $vaddr, $offset)
(vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset))),
(Instr_ADDR64 $srsrc, $vaddr, $soffset, $offset)
>;
}