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AMDGPU/SI: Remove wait state handling for SMRD in SIInsertWaits 

This was supposed to be part of r268143.

llvm-svn: 268154
This commit is contained in:
Tom Stellard 2016-04-30 04:04:48 +00:00
parent 53ca3c93db
commit c51e4468b7
3 changed files with 4 additions and 8 deletions
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6
llvm/lib/Target/AMDGPU/SIInsertWaits.cpp
View File

@ -634,12 +634,6 @@ bool SIInsertWaits::runOnMachineFunction(MachineFunction &MF) {
insertDPPWaitStates(I); insertDPPWaitStates(I);
} }
// Insert required wait states for SMRD reading an SGPR written by a VALU
// instruction.
if (ST.getGeneration() <= AMDGPUSubtarget::SOUTHERN_ISLANDS &&
I->getOpcode() == AMDGPU::V_READFIRSTLANE_B32)
TII->insertWaitStates(MBB, std::next(I), 4);
// Record pre-existing, explicitly requested waits // Record pre-existing, explicitly requested waits
if (I->getOpcode() == AMDGPU::S_WAITCNT) { if (I->getOpcode() == AMDGPU::S_WAITCNT) {
handleExistingWait(*I); handleExistingWait(*I);

3
llvm/test/CodeGen/AMDGPU/missing-store.ll
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@ -10,7 +10,8 @@
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}} ; SI: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
; SI: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}} ; SI: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
; SI-NEXT: s_nop ; SI: s_load_dword
; SI: s_nop 2
; SI: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}} ; SI: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: s_endpgm ; SI: s_endpgm

3
llvm/test/CodeGen/AMDGPU/salu-to-valu.ll
View File

@ -56,7 +56,8 @@ done: ; preds = %loop
; SI: s_movk_i32 [[OFFSET:s[0-9]+]], 0x2ee0 ; SI: s_movk_i32 [[OFFSET:s[0-9]+]], 0x2ee0
; GCN: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}} ; GCN: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}} ; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
; SI-NEXT: s_nop ; SI: s_mov_b32
; SI: s_nop 2
; SI: s_load_dword [[OUT:s[0-9]+]], s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, [[OFFSET]] ; SI: s_load_dword [[OUT:s[0-9]+]], s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, [[OFFSET]]
; CI: s_load_dword [[OUT:s[0-9]+]], s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0xbb8 ; CI: s_load_dword [[OUT:s[0-9]+]], s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0xbb8
; GCN: v_mov_b32_e32 [[V_OUT:v[0-9]+]], [[OUT]] ; GCN: v_mov_b32_e32 [[V_OUT:v[0-9]+]], [[OUT]]