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ARM: correct WoA __builtin_alloca handling on O0 

When performing a dynamic stack adjustment without optimisations, we would mark
SP as def and R4 as kill.  This occurred as part of the expansion of a
WIN__CHKSTK SDNode which indicated the proper handling of SP and R4.  The result
would be that we would double define SP as part of an operation, which is
obviously incorrect.

Furthermore, the VTList for the chain had an incorrect parameter type of i32
instead of Other.

Correct these to permit proper lowering of __builtin_alloca at -O0.

llvm-svn: 213442
This commit is contained in:
Saleem Abdulrasool 2014-07-19 01:29:51 +00:00
parent 6096d44f76
commit c4e00289a7
2 changed files with 24 additions and 3 deletions
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5
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -7227,8 +7227,7 @@ ARMTargetLowering::EmitLowered__chkstk(MachineInstr *MI,
AddDefaultCC(AddDefaultPred(BuildMI(*MBB, MI, DL, TII.get(ARM::t2SUBrr),
ARM::SP)
.addReg(ARM::SP, RegState::Define)
.addReg(ARM::R4, RegState::Kill)));
.addReg(ARM::SP).addReg(ARM::R4)));
MI->eraseFromParent();
return MBB;
@ -10622,7 +10621,7 @@ ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
Chain = DAG.getCopyToReg(Chain, DL, ARM::R4, Words, Flag);
Flag = Chain.getValue(1);
SDVTList NodeTys = DAG.getVTList(MVT::i32, MVT::Glue);
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
Chain = DAG.getNode(ARMISD::WIN__CHKSTK, DL, NodeTys, Chain, Flag);
SDValue NewSP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32);

22
llvm/test/CodeGen/ARM/Windows/alloca.ll Normal file
View File

@ -0,0 +1,22 @@
; RUN: llc -O0 -mtriple thumbv7-windows-itanium -filetype asm -o - %s | FileCheck %s
declare arm_aapcs_vfpcc i32 @num_entries()
define arm_aapcs_vfpcc void @test___builtin_alloca() {
entry:
%array = alloca i8*, align 4
%call = call arm_aapcs_vfpcc i32 @num_entries()
%mul = mul i32 4, %call
%0 = alloca i8, i32 %mul
store i8* %0, i8** %array, align 4
ret void
}
; CHECK: bl num_entries
; CHECK: movs [[R1:r[0-9]+]], #7
; CHECK: add.w [[R0:r[0-9]+]], [[R1]], [[R0]], lsl #2
; CHECK: bic [[R0]], [[R0]], #7
; CHECK: lsrs r4, [[R0]], #2
; CHECK: bl __chkstk
; CHECK: sub.w sp, sp, r4