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[CodeGen] Fix order of PHINode and MA Write generation. 

At the end of a region statement, the PHINode must be generated
while the current IRBuilder's block is the region's exit node. For
obvious reasons: The PHINode references the region's exiting block.
A partial write would insert new control flow, i.e. insert new basic
blocks between the exiting blocks and the current block.

We fix this by generating the PHI nodes (region exit values) before
generating any MemoryAccess's stores.

This should fix the AOSP buildbot.

Reported-by: Eli Friedman <efriedma@quicinc.com>
llvm-svn: 361204
This commit is contained in:
Michael Kruse 2019-05-20 22:31:09 +00:00
parent 28e351af2a
commit c4c679c232
4 changed files with 166 additions and 1 deletions
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19
polly/lib/CodeGen/BlockGenerators.cpp
View File

@ -1693,6 +1693,22 @@ void RegionGenerator::generateScalarStores(
"Block statements need to use the generateScalarStores() "
"function in the BlockGenerator");
// Get the exit scalar values before generating the writes.
// This is necessary because RegionGenerator::getExitScalar may insert
// PHINodes that depend on the region's exiting blocks. But
// BlockGenerator::generateConditionalExecution may insert a new basic block
// such that the current basic block is not a direct successor of the exiting
// blocks anymore. Hence, build the PHINodes while the current block is still
// the direct successor.
SmallDenseMap<MemoryAccess *, Value *> NewExitScalars;
for (MemoryAccess *MA : Stmt) {
if (MA->isOriginalArrayKind() || MA->isRead())
continue;
Value *NewVal = getExitScalar(MA, LTS, BBMap);
NewExitScalars[MA] = NewVal;
}
for (MemoryAccess *MA : Stmt) {
if (MA->isOriginalArrayKind() || MA->isRead())
continue;
@ -1701,7 +1717,8 @@ void RegionGenerator::generateScalarStores(
std::string Subject = MA->getId().get_name();
generateConditionalExecution(
Stmt, AccDom, Subject.c_str(), [&, this, MA]() {
Value *NewVal = getExitScalar(MA, LTS, BBMap);
Value *NewVal = NewExitScalars.lookup(MA);
assert(NewVal && "The exit scalar must be determined before");
Value *Address = getImplicitAddress(*MA, getLoopForStmt(Stmt), LTS,
BBMap, NewAccesses);
assert((!isa<Instruction>(NewVal) ||

44
polly/test/Isl/CodeGen/region_multiexit_partialwrite.ll Normal file
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@ -0,0 +1,44 @@
; RUN: opt %loadPolly -polly-import-jscop -polly-import-jscop-postfix=transformed -polly-codegen -S < %s | FileCheck %s
;
; This text case has a partial write of PHI in a region-statement. It
; requires that the new PHINode from the region's exiting block is
; generated before before the partial memory write.
;
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
define void @region_multiexit_partialwrite(i32* %arg, i64 %arg1, i32* %arg2) {
bb:
br label %bb3
bb3:
%tmp = phi i64 [ %tmp17, %bb10 ], [ 1, %bb ]
%tmp4 = getelementptr inbounds i32, i32* %arg, i64 %tmp
%tmp5 = load i32, i32* %tmp4, align 4
%tmp6 = icmp slt i32 %tmp5, 0
br i1 %tmp6, label %bb7, label %bb9
bb7:
%tmp8 = select i1 undef, i32 -2147483648, i32 undef
br label %bb10
bb9:
br label %bb10
bb10:
%tmp11 = phi i32 [ %tmp8, %bb7 ], [ undef, %bb9 ]
%tmp16 = getelementptr inbounds i32, i32* %arg2, i64 %tmp
store i32 %tmp11, i32* %tmp16, align 4
%tmp17 = add nuw i64 %tmp, 1
%tmp18 = icmp eq i64 %tmp17, %arg1
br i1 %tmp18, label %bb19, label %bb3
bb19:
ret void
}
; CHECK: polly.stmt.bb10.exit:
; CHECK-NEXT: %polly.tmp11 = phi i32 [ %p_tmp8, %polly.stmt.bb7 ], [ undef, %polly.stmt.bb9 ]
; CHECK: polly.stmt.bb10.exit.Stmt_bb3__TO__bb10_Write1.partial:
; CHECK: store i32 %polly.tmp11

52
polly/test/Isl/CodeGen/region_multiexit_partialwrite___%bb3---%bb19.jscop Normal file
View File

@ -0,0 +1,52 @@
{
"arrays": [
{
"name": "MemRef_arg",
"sizes": [
"*"
],
"type": "i32"
},
{
"name": "MemRef_arg2",
"sizes": [
"*"
],
"type": "i32"
}
],
"context": "[arg1] -> { : -9223372036854775808 <= arg1 <= 9223372036854775807 }",
"name": "%bb3---%bb19",
"statements": [
{
"accesses": [
{
"kind": "read",
"relation": "[arg1] -> { Stmt_bb3__TO__bb10[i0] -> MemRef_arg[1 + i0] }"
},
{
"kind": "write",
"relation": "[arg1] -> { Stmt_bb3__TO__bb10[i0] -> MemRef_tmp11__phi[] }"
}
],
"domain": "[arg1] -> { Stmt_bb3__TO__bb10[i0] : 0 <= i0 <= -2 + arg1 }",
"name": "Stmt_bb3__TO__bb10",
"schedule": "[arg1] -> { Stmt_bb3__TO__bb10[i0] -> [i0, 0] }"
},
{
"accesses": [
{
"kind": "read",
"relation": "[arg1] -> { Stmt_bb10[i0] -> MemRef_tmp11__phi[] }"
},
{
"kind": "write",
"relation": "[arg1] -> { Stmt_bb10[i0] -> MemRef_arg2[1 + i0] }"
}
],
"domain": "[arg1] -> { Stmt_bb10[i0] : 0 <= i0 <= -2 + arg1 }",
"name": "Stmt_bb10",
"schedule": "[arg1] -> { Stmt_bb10[i0] -> [i0, 1] }"
}
]
}

52
polly/test/Isl/CodeGen/region_multiexit_partialwrite___%bb3---%bb19.jscop.transformed Normal file
View File

@ -0,0 +1,52 @@
{
"arrays": [
{
"name": "MemRef_arg",
"sizes": [
"*"
],
"type": "i32"
},
{
"name": "MemRef_arg2",
"sizes": [
"*"
],
"type": "i32"
}
],
"context": "[arg1] -> { : -9223372036854775808 <= arg1 <= 9223372036854775807 }",
"name": "%bb3---%bb19",
"statements": [
{
"accesses": [
{
"kind": "read",
"relation": "[arg1] -> { Stmt_bb3__TO__bb10[i0] -> MemRef_arg[1 + i0] }"
},
{
"kind": "write",
"relation": "[arg1] -> { Stmt_bb3__TO__bb10[i0] -> MemRef_arg2[1 + i0] : arg1 <= 2305843009213693952 }"
}
],
"domain": "[arg1] -> { Stmt_bb3__TO__bb10[i0] : 0 <= i0 <= -2 + arg1 }",
"name": "Stmt_bb3__TO__bb10",
"schedule": "[arg1] -> { Stmt_bb3__TO__bb10[i0] -> [i0, 0] }"
},
{
"accesses": [
{
"kind": "read",
"relation": "[arg1] -> { Stmt_bb10[i0] -> MemRef_arg2[1 + i0] }"
},
{
"kind": "write",
"relation": "[arg1] -> { Stmt_bb10[i0] -> MemRef_arg2[1 + i0] }"
}
],
"domain": "[arg1] -> { Stmt_bb10[i0] : 0 <= i0 <= -2 + arg1 }",
"name": "Stmt_bb10",
"schedule": "[arg1] -> { Stmt_bb10[i0] -> [i0, 1] }"
}
]
}