forked from OSchip/llvm-project
[X86][SSE] Ensure vector partial load/stores use the WriteVecLoad/WriteVecStore scheduler classes
Retag some instructions that were missed when we split off vector load/store/moves - MOVQ/MOVD etc. Fixes BtVer2/SLM which have different behaviours for GPR stores. llvm-svn: 332718
This commit is contained in:
Simon Pilgrim
parent
a840a46557
commit
c4b8d367a8
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@ -3622,7 +3622,7 @@ def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$s
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"vmovd\t{$src, $dst|$dst, $src}",
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[(set VR128X:$dst,
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(v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
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EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteLoad]>;
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EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteVecLoad]>;
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def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
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"vmovq\t{$src, $dst|$dst, $src}",
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[(set VR128X:$dst,
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@ -3632,7 +3632,7 @@ let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
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def VMOV64toPQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
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(ins i64mem:$src),
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"vmovq\t{$src, $dst|$dst, $src}", []>,
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EVEX, VEX_W, EVEX_CD8<64, CD8VT1>, Sched<[WriteLoad]>;
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EVEX, VEX_W, EVEX_CD8<64, CD8VT1>, Sched<[WriteVecLoad]>;
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let isCodeGenOnly = 1 in {
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def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64X:$dst), (ins GR64:$src),
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"vmovq\t{$src, $dst|$dst, $src}",
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@ -3641,7 +3641,7 @@ def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64X:$dst), (ins GR64:$src)
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def VMOV64toSDZrm : AVX512XSI<0x7E, MRMSrcMem, (outs FR64X:$dst), (ins i64mem:$src),
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"vmovq\t{$src, $dst|$dst, $src}",
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[(set FR64X:$dst, (bitconvert (loadi64 addr:$src)))]>,
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EVEX, VEX_W, EVEX_CD8<8, CD8VT8>, Sched<[WriteLoad]>;
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EVEX, VEX_W, EVEX_CD8<8, CD8VT8>, Sched<[WriteVecLoad]>;
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def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64X:$src),
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"vmovq\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (bitconvert FR64X:$src))]>,
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@ -3649,7 +3649,7 @@ def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64X:$src
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def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64X:$src),
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"vmovq\t{$src, $dst|$dst, $src}",
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[(store (i64 (bitconvert FR64X:$src)), addr:$dst)]>,
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EVEX, VEX_W, Sched<[WriteStore]>,
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EVEX, VEX_W, Sched<[WriteVecStore]>,
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EVEX_CD8<64, CD8VT1>;
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}
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} // ExeDomain = SSEPackedInt
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@ -3665,7 +3665,7 @@ def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src)
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def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
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"vmovd\t{$src, $dst|$dst, $src}",
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[(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))]>,
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EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteLoad]>;
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EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteVecLoad]>;
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} // ExeDomain = SSEPackedInt, isCodeGenOnly = 1
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// Move doubleword from xmm register to r/m32
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@ -3681,7 +3681,7 @@ def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
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"vmovd\t{$src, $dst|$dst, $src}",
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[(store (i32 (extractelt (v4i32 VR128X:$src),
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(iPTR 0))), addr:$dst)]>,
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EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteStore]>;
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EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteVecStore]>;
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} // ExeDomain = SSEPackedInt
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// Move quadword from xmm1 register to r/m64
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@ -3697,7 +3697,7 @@ def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
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let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
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def VMOVPQIto64Zmr : I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR128X:$src),
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"vmovq\t{$src, $dst|$dst, $src}", []>, PD,
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EVEX, VEX_W, Sched<[WriteStore]>,
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EVEX, VEX_W, Sched<[WriteVecStore]>,
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Requires<[HasAVX512, In64BitMode]>;
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def VMOVPQI2QIZmr : I<0xD6, MRMDestMem, (outs),
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@ -3706,7 +3706,7 @@ def VMOVPQI2QIZmr : I<0xD6, MRMDestMem, (outs),
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[(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
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addr:$dst)]>,
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EVEX, PD, VEX_W, EVEX_CD8<64, CD8VT1>,
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Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
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Sched<[WriteVecStore]>, Requires<[HasAVX512, In64BitMode]>;
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let hasSideEffects = 0 in
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def VMOVPQI2QIZrr : AVX512BI<0xD6, MRMDestReg, (outs VR128X:$dst),
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@ -3727,7 +3727,7 @@ def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
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(ins i32mem:$dst, FR32X:$src),
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"vmovd\t{$src, $dst|$dst, $src}",
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[(store (i32 (bitconvert FR32X:$src)), addr:$dst)]>,
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EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteStore]>;
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EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteVecStore]>;
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} // ExeDomain = SSEPackedInt, isCodeGenOnly = 1
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// Move Quadword Int to Packed Quadword Int
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@ -3738,7 +3738,7 @@ def VMOVQI2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
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"vmovq\t{$src, $dst|$dst, $src}",
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[(set VR128X:$dst,
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(v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
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EVEX, VEX_W, EVEX_CD8<8, CD8VT8>, Sched<[WriteLoad]>;
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EVEX, VEX_W, EVEX_CD8<8, CD8VT8>, Sched<[WriteVecLoad]>;
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} // ExeDomain = SSEPackedInt
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// Allow "vmovd" but print "vmovq".
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@ -170,7 +170,7 @@ def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
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"movd\t{$src, $dst|$dst, $src}",
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[(set VR64:$dst,
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(x86mmx (scalar_to_vector (loadi32 addr:$src))))]>,
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Sched<[WriteLoad]>;
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Sched<[WriteVecLoad]>;
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let Predicates = [HasMMX] in {
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let AddedComplexity = 15 in
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@ -187,7 +187,7 @@ let Predicates = [HasMMX] in {
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let mayStore = 1 in
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def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
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"movd\t{$src, $dst|$dst, $src}", []>,
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Sched<[WriteStore]>;
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Sched<[WriteVecStore]>;
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def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR64:$src),
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"movd\t{$src, $dst|$dst, $src}",
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@ -3970,7 +3970,7 @@ def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
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"movd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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(v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
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VEX, Sched<[WriteLoad]>;
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VEX, Sched<[WriteVecLoad]>;
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def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
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"movq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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@ -3979,7 +3979,7 @@ def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
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let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
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def VMOV64toPQIrm : VRS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
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"movq\t{$src, $dst|$dst, $src}", []>,
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VEX, Sched<[WriteLoad]>;
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VEX, Sched<[WriteVecLoad]>;
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let isCodeGenOnly = 1 in
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def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
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"movq\t{$src, $dst|$dst, $src}",
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@ -3995,7 +3995,7 @@ def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
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"movd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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(v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
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Sched<[WriteLoad]>;
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Sched<[WriteVecLoad]>;
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def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
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"movq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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@ -4004,7 +4004,7 @@ def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
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let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
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def MOV64toPQIrm : RS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
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"movq\t{$src, $dst|$dst, $src}", []>,
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Sched<[WriteLoad]>;
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Sched<[WriteVecLoad]>;
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let isCodeGenOnly = 1 in
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def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
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"movq\t{$src, $dst|$dst, $src}",
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@ -4024,7 +4024,7 @@ let ExeDomain = SSEPackedInt, isCodeGenOnly = 1 in {
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def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
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"movd\t{$src, $dst|$dst, $src}",
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[(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
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VEX, Sched<[WriteLoad]>;
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VEX, Sched<[WriteVecLoad]>;
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def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
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"movd\t{$src, $dst|$dst, $src}",
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[(set FR32:$dst, (bitconvert GR32:$src))]>,
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@ -4033,7 +4033,7 @@ let ExeDomain = SSEPackedInt, isCodeGenOnly = 1 in {
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def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
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"movd\t{$src, $dst|$dst, $src}",
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[(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
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Sched<[WriteLoad]>;
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Sched<[WriteVecLoad]>;
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} // ExeDomain = SSEPackedInt, isCodeGenOnly = 1
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//===---------------------------------------------------------------------===//
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@ -4050,7 +4050,7 @@ def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
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"movd\t{$src, $dst|$dst, $src}",
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[(store (i32 (extractelt (v4i32 VR128:$src),
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(iPTR 0))), addr:$dst)]>,
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VEX, Sched<[WriteStore]>;
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VEX, Sched<[WriteVecStore]>;
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def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
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"movd\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (extractelt (v4i32 VR128:$src),
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@ -4060,7 +4060,7 @@ def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
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"movd\t{$src, $dst|$dst, $src}",
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[(store (i32 (extractelt (v4i32 VR128:$src),
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(iPTR 0))), addr:$dst)]>,
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Sched<[WriteStore]>;
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Sched<[WriteVecStore]>;
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} // ExeDomain = SSEPackedInt
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//===---------------------------------------------------------------------===//
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@ -4084,11 +4084,11 @@ let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
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def VMOVPQIto64mr : VRS2I<0x7E, MRMDestMem, (outs),
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(ins i64mem:$dst, VR128:$src),
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"movq\t{$src, $dst|$dst, $src}", []>,
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VEX, Sched<[WriteStore]>;
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VEX, Sched<[WriteVecStore]>;
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let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
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def MOVPQIto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
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"movq\t{$src, $dst|$dst, $src}", []>,
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Sched<[WriteStore]>;
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Sched<[WriteVecStore]>;
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} // ExeDomain = SSEPackedInt
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//===---------------------------------------------------------------------===//
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@ -4099,7 +4099,7 @@ let ExeDomain = SSEPackedInt, isCodeGenOnly = 1 in {
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def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
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"movq\t{$src, $dst|$dst, $src}",
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[(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
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VEX, Sched<[WriteLoad]>;
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VEX, Sched<[WriteVecLoad]>;
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def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
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"movq\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (bitconvert FR64:$src))]>,
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@ -4107,12 +4107,12 @@ let ExeDomain = SSEPackedInt, isCodeGenOnly = 1 in {
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def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
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"movq\t{$src, $dst|$dst, $src}",
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[(store (i64 (bitconvert FR64:$src)), addr:$dst)]>,
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VEX, Sched<[WriteStore]>;
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VEX, Sched<[WriteVecStore]>;
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def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
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"movq\t{$src, $dst|$dst, $src}",
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[(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
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Sched<[WriteLoad]>;
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Sched<[WriteVecLoad]>;
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def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
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"movq\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (bitconvert FR64:$src))]>,
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@ -4120,7 +4120,7 @@ let ExeDomain = SSEPackedInt, isCodeGenOnly = 1 in {
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def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
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"movq\t{$src, $dst|$dst, $src}",
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[(store (i64 (bitconvert FR64:$src)), addr:$dst)]>,
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Sched<[WriteStore]>;
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Sched<[WriteVecStore]>;
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} // ExeDomain = SSEPackedInt, isCodeGenOnly = 1
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//===---------------------------------------------------------------------===//
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@ -4134,7 +4134,7 @@ let ExeDomain = SSEPackedInt, isCodeGenOnly = 1 in {
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def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
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"movd\t{$src, $dst|$dst, $src}",
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[(store (i32 (bitconvert FR32:$src)), addr:$dst)]>,
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VEX, Sched<[WriteStore]>;
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VEX, Sched<[WriteVecStore]>;
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def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
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"movd\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (bitconvert FR32:$src))]>,
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@ -4142,7 +4142,7 @@ let ExeDomain = SSEPackedInt, isCodeGenOnly = 1 in {
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def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
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"movd\t{$src, $dst|$dst, $src}",
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[(store (i32 (bitconvert FR32:$src)), addr:$dst)]>,
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Sched<[WriteStore]>;
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Sched<[WriteVecStore]>;
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} // ExeDomain = SSEPackedInt, isCodeGenOnly = 1
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let Predicates = [UseAVX] in {
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@ -4225,7 +4225,7 @@ def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
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// Move Quadword Int to Packed Quadword Int
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//
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let ExeDomain = SSEPackedInt, SchedRW = [WriteLoad] in {
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let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLoad] in {
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def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
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"vmovq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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@ -4241,7 +4241,7 @@ def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
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//===---------------------------------------------------------------------===//
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// Move Packed Quadword Int to Quadword Int
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//
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let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
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let ExeDomain = SSEPackedInt, SchedRW = [WriteVecStore] in {
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def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
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"movq\t{$src, $dst|$dst, $src}",
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[(store (i64 (extractelt (v2i64 VR128:$src),
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@ -600,13 +600,7 @@ def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
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let ResourceCycles = [1,1];
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}
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def: InstRW<[BWWriteResGroup10], (instregex "FBSTPm",
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"MMX_MOVD64mr",
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"ST_FP(32|64|80)m",
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"(V?)MOV(H|L)(PD|PS)mr",
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"(V?)MOVPDI2DImr",
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"(V?)MOVPQI2QImr",
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"(V?)MOVPQIto64mr",
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"(V?)MOV(SD|SS)mr")>;
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"ST_FP(32|64|80)m")>;
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def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {
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let Latency = 2;
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@ -786,13 +786,7 @@ def HWWriteResGroup1 : SchedWriteRes<[HWPort4,HWPort237]> {
|
|||
let ResourceCycles = [1,1];
|
||||
}
|
||||
def: InstRW<[HWWriteResGroup1], (instregex "FBSTPm",
|
||||
"MMX_MOVD64mr",
|
||||
"ST_FP(32|64|80)m",
|
||||
"(V?)MOV(H|L)(PD|PS)mr",
|
||||
"(V?)MOVPDI2DImr",
|
||||
"(V?)MOVPQI2QImr",
|
||||
"(V?)MOVPQIto64mr",
|
||||
"(V?)MOV(SD|SS)mr",
|
||||
"VMPTRSTm")>;
|
||||
|
||||
def HWWriteResGroup2 : SchedWriteRes<[HWPort0]> {
|
||||
|
|
|
|||
|
|
@ -602,13 +602,7 @@ def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> {
|
|||
let ResourceCycles = [1,1];
|
||||
}
|
||||
def: InstRW<[SKLWriteResGroup11], (instregex "FBSTPm",
|
||||
"MMX_MOVD64mr",
|
||||
"ST_FP(32|64|80)m",
|
||||
"(V?)MOV(H|L)(PD|PS)mr",
|
||||
"(V?)MOVPDI2DImr",
|
||||
"(V?)MOVPQI2QImr",
|
||||
"(V?)MOVPQIto64mr",
|
||||
"(V?)MOV(SD|SS)mr",
|
||||
"VMPTRSTm")>;
|
||||
|
||||
def SKLWriteResGroup12 : SchedWriteRes<[SKLPort0]> {
|
||||
|
|
|
|||
|
|
@ -627,17 +627,7 @@ def SKXWriteResGroup11 : SchedWriteRes<[SKXPort4,SKXPort237]> {
|
|||
}
|
||||
def: InstRW<[SKXWriteResGroup11], (instregex "FBSTPm",
|
||||
"KMOV(B|D|Q|W)mk",
|
||||
"MMX_MOVD64mr",
|
||||
"ST_FP(32|64|80)m",
|
||||
"VMOV(H|L)(PD|PS)Z128mr(b?)",
|
||||
"(V?)MOV(H|L)(PD|PS)mr",
|
||||
"VMOVPDI2DIZmr(b?)",
|
||||
"(V?)MOVPDI2DImr",
|
||||
"VMOVPQI(2QI|to64)Zmr(b?)",
|
||||
"(V?)MOVPQI2QImr",
|
||||
"(V?)MOVPQIto64mr",
|
||||
"VMOV(SD|SS)Zmr(b?)",
|
||||
"(V?)MOV(SD|SS)mr",
|
||||
"VMPTRSTm")>;
|
||||
|
||||
def SKXWriteResGroup12 : SchedWriteRes<[SKXPort0]> {
|
||||
|
|
|
|||
|
|
@ -1720,7 +1720,7 @@ vzeroupper
|
|||
|
||||
# CHECK: Resource pressure per iteration:
|
||||
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
|
||||
# CHECK-NEXT: 48.00 2.00 - 350.50 910.50 398.00 418.00 382.00 - 43.00 130.00 118.50 118.50 38.00
|
||||
# CHECK-NEXT: 48.00 2.00 - 350.50 910.50 399.00 421.00 382.00 - 43.00 132.00 119.50 119.50 38.00
|
||||
|
||||
# CHECK: Resource pressure by instruction:
|
||||
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions:
|
||||
|
|
@ -1959,9 +1959,9 @@ vzeroupper
|
|||
# CHECK-NEXT: - - - - - - 1.00 - - 1.00 1.00 - - - vmovaps %ymm0, (%rax)
|
||||
# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 1.00 - - - - - - vmovaps (%rax), %ymm2
|
||||
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - vmovd %eax, %xmm2
|
||||
# CHECK-NEXT: - - - - - - - 1.00 - - - - - - vmovd (%rax), %xmm2
|
||||
# CHECK-NEXT: - - - - - 0.50 0.50 1.00 - - - 0.50 0.50 - vmovd (%rax), %xmm2
|
||||
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - vmovd %xmm0, %ecx
|
||||
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - vmovd %xmm0, (%rax)
|
||||
# CHECK-NEXT: - - - - - - 1.00 - - 1.00 1.00 - - - vmovd %xmm0, (%rax)
|
||||
# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - vmovddup %xmm0, %xmm2
|
||||
# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 1.00 - - - - - - vmovddup (%rax), %xmm2
|
||||
# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - vmovddup %ymm0, %ymm2
|
||||
|
|
@ -2002,9 +2002,9 @@ vzeroupper
|
|||
# CHECK-NEXT: - - - - - - 2.00 - - 2.00 2.00 - - - vmovntps %ymm0, (%rax)
|
||||
# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - vmovq %xmm0, %xmm2
|
||||
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - vmovq %rax, %xmm2
|
||||
# CHECK-NEXT: - - - - - - - 1.00 - - - - - - vmovq (%rax), %xmm2
|
||||
# CHECK-NEXT: - - - - - 0.50 0.50 1.00 - - - 0.50 0.50 - vmovq (%rax), %xmm2
|
||||
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - vmovq %xmm0, %rcx
|
||||
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - vmovq %xmm0, (%rax)
|
||||
# CHECK-NEXT: - - - - - - 1.00 - - 1.00 1.00 - - - vmovq %xmm0, (%rax)
|
||||
# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - vmovsd %xmm0, %xmm1, %xmm2
|
||||
# CHECK-NEXT: - - - - - - 1.00 - - 1.00 1.00 - - - vmovsd %xmm0, (%rax)
|
||||
# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 1.00 - - - - - - vmovsd (%rax), %xmm2
|
||||
|
|
|
|||
|
|
@ -288,15 +288,15 @@ pxor (%rax), %mm2
|
|||
|
||||
# CHECK: Resource pressure per iteration:
|
||||
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
|
||||
# CHECK-NEXT: 2.00 2.00 - 0.50 0.50 52.00 47.00 46.00 - 2.00 1.00 45.50 45.50 6.00
|
||||
# CHECK-NEXT: 2.00 2.00 - 0.50 0.50 52.50 48.50 46.00 - 2.00 2.00 46.00 46.00 6.00
|
||||
|
||||
# CHECK: Resource pressure by instruction:
|
||||
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions:
|
||||
# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - emms
|
||||
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movd %eax, %mm2
|
||||
# CHECK-NEXT: - - - - - - - 1.00 - - - - - - movd (%rax), %mm2
|
||||
# CHECK-NEXT: - - - - - 0.50 0.50 1.00 - - - 0.50 0.50 - movd (%rax), %mm2
|
||||
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movd %mm0, %ecx
|
||||
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - movd %mm0, (%rax)
|
||||
# CHECK-NEXT: - - - - - - 1.00 - - 1.00 1.00 - - - movd %mm0, (%rax)
|
||||
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movq %rax, %mm2
|
||||
# CHECK-NEXT: - - - - - 0.50 0.50 1.00 - - - 0.50 0.50 - movq (%rax), %mm2
|
||||
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movq %mm0, %rcx
|
||||
|
|
|
|||
|
|
@ -685,7 +685,7 @@ xorpd (%rax), %xmm2
|
|||
|
||||
# CHECK: Resource pressure per iteration:
|
||||
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
|
||||
# CHECK-NEXT: 17.00 2.00 - 46.00 203.00 115.50 136.50 117.00 - 15.00 52.00 65.50 65.50 12.00
|
||||
# CHECK-NEXT: 17.00 2.00 - 46.00 203.00 116.50 139.50 117.00 - 15.00 54.00 66.50 66.50 12.00
|
||||
|
||||
# CHECK: Resource pressure by instruction:
|
||||
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions:
|
||||
|
|
@ -760,9 +760,9 @@ xorpd (%rax), %xmm2
|
|||
# CHECK-NEXT: - - - - - - 1.00 - - 1.00 1.00 - - - movapd %xmm0, (%rax)
|
||||
# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 1.00 - - - - - - movapd (%rax), %xmm2
|
||||
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movd %eax, %xmm2
|
||||
# CHECK-NEXT: - - - - - - - 1.00 - - - - - - movd (%rax), %xmm2
|
||||
# CHECK-NEXT: - - - - - 0.50 0.50 1.00 - - - 0.50 0.50 - movd (%rax), %xmm2
|
||||
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movd %xmm0, %ecx
|
||||
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - movd %xmm0, (%rax)
|
||||
# CHECK-NEXT: - - - - - - 1.00 - - 1.00 1.00 - - - movd %xmm0, (%rax)
|
||||
# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - movdqa %xmm0, %xmm2
|
||||
# CHECK-NEXT: - - - - - - 1.00 - - 1.00 1.00 - - - movdqa %xmm0, (%rax)
|
||||
# CHECK-NEXT: - - - - - 0.50 0.50 1.00 - - - 0.50 0.50 - movdqa (%rax), %xmm2
|
||||
|
|
@ -781,9 +781,9 @@ xorpd (%rax), %xmm2
|
|||
# CHECK-NEXT: - - - - - - 1.00 - - 1.00 1.00 - - - movntpd %xmm0, (%rax)
|
||||
# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - movq %xmm0, %xmm2
|
||||
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movq %rax, %xmm2
|
||||
# CHECK-NEXT: - - - - - - - 1.00 - - - - - - movq (%rax), %xmm2
|
||||
# CHECK-NEXT: - - - - - 0.50 0.50 1.00 - - - 0.50 0.50 - movq (%rax), %xmm2
|
||||
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movq %xmm0, %rcx
|
||||
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - movq %xmm0, (%rax)
|
||||
# CHECK-NEXT: - - - - - - 1.00 - - 1.00 1.00 - - - movq %xmm0, (%rax)
|
||||
# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - movq2dq %mm0, %xmm2
|
||||
# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - movsd %xmm0, %xmm2
|
||||
# CHECK-NEXT: - - - - - - 1.00 - - 1.00 1.00 - - - movsd %xmm0, (%rax)
|
||||
|
|
|
|||
|
|
@ -282,7 +282,7 @@ pxor (%rax), %mm2
|
|||
|
||||
# CHECK: Resource pressure per iteration:
|
||||
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
|
||||
# CHECK-NEXT: - - - 77.00 29.00 2.50 2.50 48.00
|
||||
# CHECK-NEXT: - - - 77.00 29.00 2.00 2.00 48.00
|
||||
|
||||
# CHECK: Resource pressure by instruction:
|
||||
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
|
||||
|
|
@ -290,7 +290,7 @@ pxor (%rax), %mm2
|
|||
# CHECK-NEXT: - - - - - 0.50 0.50 - movd %eax, %mm2
|
||||
# CHECK-NEXT: - - - - - - - 1.00 movd (%rax), %mm2
|
||||
# CHECK-NEXT: - - - - - 0.50 0.50 - movd %mm0, %ecx
|
||||
# CHECK-NEXT: - - - - - 0.50 0.50 1.00 movd %mm0, (%rax)
|
||||
# CHECK-NEXT: - - - - - - - 1.00 movd %mm0, (%rax)
|
||||
# CHECK-NEXT: - - - - - 0.50 0.50 - movq %rax, %mm2
|
||||
# CHECK-NEXT: - - - - - - - 1.00 movq (%rax), %mm2
|
||||
# CHECK-NEXT: - - - - - 0.50 0.50 - movq %mm0, %rcx
|
||||
|
|
|
|||
|
|
@ -679,7 +679,7 @@ xorpd (%rax), %xmm2
|
|||
|
||||
# CHECK: Resource pressure per iteration:
|
||||
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
|
||||
# CHECK-NEXT: - 412.00 8.00 150.50 86.50 4.00 4.00 132.00
|
||||
# CHECK-NEXT: - 412.00 8.00 150.50 86.50 3.00 3.00 132.00
|
||||
|
||||
# CHECK: Resource pressure by instruction:
|
||||
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
|
||||
|
|
@ -756,7 +756,7 @@ xorpd (%rax), %xmm2
|
|||
# CHECK-NEXT: - - - - - 0.50 0.50 - movd %eax, %xmm2
|
||||
# CHECK-NEXT: - - - - - - - 1.00 movd (%rax), %xmm2
|
||||
# CHECK-NEXT: - - - - - 0.50 0.50 - movd %xmm0, %ecx
|
||||
# CHECK-NEXT: - - - - - 0.50 0.50 1.00 movd %xmm0, (%rax)
|
||||
# CHECK-NEXT: - - - - - - - 1.00 movd %xmm0, (%rax)
|
||||
# CHECK-NEXT: - - - 0.50 0.50 - - - movdqa %xmm0, %xmm2
|
||||
# CHECK-NEXT: - - - - - - - 1.00 movdqa %xmm0, (%rax)
|
||||
# CHECK-NEXT: - - - - - - - 1.00 movdqa (%rax), %xmm2
|
||||
|
|
@ -777,7 +777,7 @@ xorpd (%rax), %xmm2
|
|||
# CHECK-NEXT: - - - - - 0.50 0.50 - movq %rax, %xmm2
|
||||
# CHECK-NEXT: - - - - - - - 1.00 movq (%rax), %xmm2
|
||||
# CHECK-NEXT: - - - - - 0.50 0.50 - movq %xmm0, %rcx
|
||||
# CHECK-NEXT: - - - - - 0.50 0.50 1.00 movq %xmm0, (%rax)
|
||||
# CHECK-NEXT: - - - - - - - 1.00 movq %xmm0, (%rax)
|
||||
# CHECK-NEXT: - - - 0.50 0.50 - - - movq2dq %mm0, %xmm2
|
||||
# CHECK-NEXT: - - - 1.00 - - - - movsd %xmm0, %xmm2
|
||||
# CHECK-NEXT: - - - - - - - 1.00 movsd %xmm0, (%rax)
|
||||
|
|
|
|||
Loading…
Reference in New Issue