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[X86] Add the debug registers DR8-DR15 so we can assemble and disassemble references to them. 

llvm-svn: 224862
This commit is contained in:
Craig Topper 2014-12-26 18:20:05 +00:00
parent d5b39237a1
commit c4b12166f2
4 changed files with 27 additions and 11 deletions
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2
llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
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@ -1453,8 +1453,6 @@ static int readModRM(struct InternalInstruction* insn) {
*valid = 0; \
return prefix##_ES + index; \
case TYPE_DEBUGREG: \
if (index > 7) \
*valid = 0; \
return prefix##_DR0 + index; \
case TYPE_CONTROLREG: \
return prefix##_CR0 + index; \

10
llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
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@ -341,7 +341,15 @@ namespace X86Disassembler {
ENTRY(DR4) \
ENTRY(DR5) \
ENTRY(DR6) \
ENTRY(DR7)
ENTRY(DR7) \
ENTRY(DR8) \
ENTRY(DR9) \
ENTRY(DR10) \
ENTRY(DR11) \
ENTRY(DR12) \
ENTRY(DR13) \
ENTRY(DR14) \
ENTRY(DR15)
#define REGS_CONTROL \
ENTRY(CR0) \

24
llvm/lib/Target/X86/X86RegisterInfo.td
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@ -263,14 +263,22 @@ def FS : X86Reg<"fs", 4>;
def GS : X86Reg<"gs", 5>;
// Debug registers
def DR0 : X86Reg<"dr0", 0>;
def DR1 : X86Reg<"dr1", 1>;
def DR2 : X86Reg<"dr2", 2>;
def DR3 : X86Reg<"dr3", 3>;
def DR4 : X86Reg<"dr4", 4>;
def DR5 : X86Reg<"dr5", 5>;
def DR6 : X86Reg<"dr6", 6>;
def DR7 : X86Reg<"dr7", 7>;
def DR0 : X86Reg<"dr0", 0>;
def DR1 : X86Reg<"dr1", 1>;
def DR2 : X86Reg<"dr2", 2>;
def DR3 : X86Reg<"dr3", 3>;
def DR4 : X86Reg<"dr4", 4>;
def DR5 : X86Reg<"dr5", 5>;
def DR6 : X86Reg<"dr6", 6>;
def DR7 : X86Reg<"dr7", 7>;
def DR8 : X86Reg<"dr8", 8>;
def DR9 : X86Reg<"dr9", 9>;
def DR10 : X86Reg<"dr10", 10>;
def DR11 : X86Reg<"dr11", 11>;
def DR12 : X86Reg<"dr12", 12>;
def DR13 : X86Reg<"dr13", 13>;
def DR14 : X86Reg<"dr14", 14>;
def DR15 : X86Reg<"dr15", 15>;
// Control registers
def CR0 : X86Reg<"cr0", 0>;

2
llvm/test/MC/Disassembler/X86/prefixes.txt
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@ -58,6 +58,8 @@
# Test that we can disassembler control registers above CR8
# CHECK: movq %cr15, %rax
0x44 0x0f 0x20 0xf8
# CHECK: movq %dr15, %rax
0x44 0x0f 0x21 0xf8
# Test that MMX ignore REX.R and REX.B.
# CHECK: movq %mm0, %mm1