forked from OSchip/llvm-project
[GlobalISel][AArch64] Add instruction selection support for @llvm.log10
This adds instruction selection support for @llvm.log10 in AArch64. It teaches GISel to lower it to a library call, updates the relevant tests, and adds a legalizer test for log10. https://reviews.llvm.org/D57341 llvm-svn: 352418
This commit is contained in:
Jessica Paquette
parent
c56779b5fc
commit
c49428a97d
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@ -130,6 +130,10 @@ static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
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assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
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return Size == 128 ? RTLIB::COS_F128
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: Size == 64 ? RTLIB::COS_F64 : RTLIB::COS_F32;
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case TargetOpcode::G_FLOG10:
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assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
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return Size == 128 ? RTLIB::LOG10_F128
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: Size == 64 ? RTLIB::LOG10_F64 : RTLIB::LOG10_F32;
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}
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llvm_unreachable("Unknown libcall function");
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}
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@ -223,7 +227,8 @@ LegalizerHelper::libcall(MachineInstr &MI) {
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case TargetOpcode::G_FPOW:
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case TargetOpcode::G_FREM:
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case TargetOpcode::G_FCOS:
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case TargetOpcode::G_FSIN: {
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case TargetOpcode::G_FSIN:
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case TargetOpcode::G_FLOG10: {
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if (Size > 64) {
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LLVM_DEBUG(dbgs() << "Size " << Size << " too large to legalize.\n");
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return UnableToLegalize;
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@ -1084,6 +1089,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
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case TargetOpcode::G_FCEIL:
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case TargetOpcode::G_FCOS:
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case TargetOpcode::G_FSIN:
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case TargetOpcode::G_FLOG10:
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assert(TypeIdx == 0);
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Observer.changingInstr(MI);
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@ -143,7 +143,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
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[=](const LegalityQuery &Query) { return std::make_pair(0, s32); })
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.legalFor({s16, s32, s64, v2s32, v4s32, v2s64, v2s16, v4s16, v8s16});
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getActionDefinitionsBuilder({G_FCOS, G_FSIN})
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getActionDefinitionsBuilder({G_FCOS, G_FSIN, G_FLOG10})
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// We need a call for these, so we always need to scalarize.
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.scalarize(0)
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// Regardless of FP16 support, widen 16-bit elements to 32-bits.
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@ -395,6 +395,7 @@ static bool isPreISelGenericFloatingPointOpcode(unsigned Opc) {
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case TargetOpcode::G_FNEG:
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case TargetOpcode::G_FCOS:
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case TargetOpcode::G_FSIN:
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case TargetOpcode::G_FLOG10:
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return true;
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}
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return false;
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@ -0,0 +1,227 @@
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# RUN: llc -verify-machineinstrs -mtriple aarch64--- \
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# RUN: -run-pass=legalizer -mattr=+fullfp16 -global-isel %s -o - \
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# RUN: | FileCheck %s
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...
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---
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name: test_v4f16.log10
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_v4f16.log10
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; CHECK: [[V1:%[0-9]+]]:_(s16), [[V2:%[0-9]+]]:_(s16), [[V3:%[0-9]+]]:_(s16), [[V4:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s16>)
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; CHECK-DAG: [[V1_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V1]](s16)
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; CHECK-NEXT: ADJCALLSTACKDOWN
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; CHECK-NEXT: $s0 = COPY [[V1_S32]](s32)
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; CHECK-NEXT: BL &log10
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; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK-NEXT: ADJCALLSTACKUP
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; CHECK-NEXT: [[ELT1:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT1_S32]](s32)
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; CHECK-DAG: [[V2_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V2]](s16)
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; CHECK-NEXT: ADJCALLSTACKDOWN
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; CHECK-NEXT: $s0 = COPY [[V2_S32]](s32)
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; CHECK-NEXT: BL &log10
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; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK-NEXT: ADJCALLSTACKUP
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; CHECK-NEXT: [[ELT2:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT2_S32]](s32)
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; CHECK-DAG: [[V3_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V3]](s16)
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; CHECK-NEXT: ADJCALLSTACKDOWN
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; CHECK-NEXT: $s0 = COPY [[V3_S32]](s32)
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; CHECK-NEXT: BL &log10
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; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK-NEXT: ADJCALLSTACKUP
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; CHECK-NEXT: [[ELT3:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT3_S32]](s32)
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; CHECK-DAG: [[V4_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V4]](s16)
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; CHECK-NEXT: ADJCALLSTACKDOWN
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; CHECK-NEXT: $s0 = COPY [[V4_S32]](s32)
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; CHECK-NEXT: BL &log10
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; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK-NEXT: ADJCALLSTACKUP
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; CHECK-NEXT: [[ELT4:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT4_S32]](s32)
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; CHECK-DAG: %{{[0-9]+}}:_(<4 x s16>) = G_BUILD_VECTOR [[ELT1]](s16), [[ELT2]](s16), [[ELT3]](s16), [[ELT4]](s16)
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%0:_(<4 x s16>) = COPY $d0
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%1:_(<4 x s16>) = G_FLOG10 %0
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$d0 = COPY %1(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_v8f16.log10
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: test_v8f16.log10
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; This is big, so let's just check for the 8 calls to log10, the the
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; G_UNMERGE_VALUES, and the G_BUILD_VECTOR. The other instructions ought
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; to be covered by the other tests.
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; CHECK: G_UNMERGE_VALUES
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; CHECK: BL &log10
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; CHECK: BL &log10
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; CHECK: BL &log10
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; CHECK: BL &log10
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; CHECK: BL &log10
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; CHECK: BL &log10
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; CHECK: BL &log10
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; CHECK: BL &log10
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; CHECK-DAG: G_BUILD_VECTOR
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%0:_(<8 x s16>) = COPY $q0
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%1:_(<8 x s16>) = G_FLOG10 %0
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$q0 = COPY %1(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_v2f32.log10
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_v2f32.log10
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; CHECK: [[V1:%[0-9]+]]:_(s32), [[V2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES %{{[0-9]+}}(<2 x s32>)
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; CHECK-NEXT: ADJCALLSTACKDOWN
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; CHECK-DAG: $s0 = COPY [[V1]](s32)
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; CHECK-DAG: BL &log10
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; CHECK-DAG: [[ELT1:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK-DAG: ADJCALLSTACKUP
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; CHECK-DAG: ADJCALLSTACKDOWN
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; CHECK-DAG: $s0 = COPY [[V2]](s32)
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; CHECK-DAG: BL &log10
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; CHECK-DAG: [[ELT2:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK-DAG: ADJCALLSTACKUP
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; CHECK-DAG: %1:_(<2 x s32>) = G_BUILD_VECTOR [[ELT1]](s32), [[ELT2]](s32)
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%0:_(<2 x s32>) = COPY $d0
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%1:_(<2 x s32>) = G_FLOG10 %0
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$d0 = COPY %1(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_v4f32.log10
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: test_v4f32.log10
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; CHECK: [[V1:%[0-9]+]]:_(s32), [[V2:%[0-9]+]]:_(s32), [[V3:%[0-9]+]]:_(s32), [[V4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s32>)
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; CHECK-NEXT: ADJCALLSTACKDOWN
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; CHECK-DAG: $s0 = COPY [[V1]](s32)
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; CHECK-DAG: BL &log10
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; CHECK-DAG: [[ELT1:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK-DAG: ADJCALLSTACKUP
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; CHECK-DAG: ADJCALLSTACKDOWN
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; CHECK-DAG: $s0 = COPY [[V2]](s32)
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; CHECK-DAG: BL &log10
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; CHECK-DAG: [[ELT2:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK-DAG: ADJCALLSTACKUP
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; CHECK-DAG: ADJCALLSTACKDOWN
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; CHECK-DAG: $s0 = COPY [[V3]](s32)
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; CHECK-DAG: BL &log10
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; CHECK-DAG: [[ELT3:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK-DAG: ADJCALLSTACKUP
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; CHECK-DAG: ADJCALLSTACKDOWN
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; CHECK-DAG: $s0 = COPY [[V4]](s32)
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; CHECK-DAG: BL &log10
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; CHECK-DAG: [[ELT4:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK-DAG: ADJCALLSTACKUP
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; CHECK-DAG: %1:_(<4 x s32>) = G_BUILD_VECTOR [[ELT1]](s32), [[ELT2]](s32), [[ELT3]](s32), [[ELT4]](s32)
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%0:_(<4 x s32>) = COPY $q0
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%1:_(<4 x s32>) = G_FLOG10 %0
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$q0 = COPY %1(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_v2f64.log10
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: test_v2f64.log10
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; CHECK: [[V1:%[0-9]+]]:_(s64), [[V2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %{{[0-9]+}}(<2 x s64>)
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; CHECK-NEXT: ADJCALLSTACKDOWN
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; CHECK-DAG: $d0 = COPY [[V1]](s64)
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; CHECK-DAG: BL &log10
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; CHECK-DAG: [[ELT1:%[0-9]+]]:_(s64) = COPY $d0
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; CHECK-DAG: ADJCALLSTACKUP
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; CHECK-DAG: ADJCALLSTACKDOWN
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; CHECK-DAG: $d0 = COPY [[V2]](s64)
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; CHECK-DAG: BL &log10
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; CHECK-DAG: [[ELT2:%[0-9]+]]:_(s64) = COPY $d0
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; CHECK-DAG: ADJCALLSTACKUP
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; CHECK-DAG: %1:_(<2 x s64>) = G_BUILD_VECTOR [[ELT1]](s64), [[ELT2]](s64)
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%0:_(<2 x s64>) = COPY $q0
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%1:_(<2 x s64>) = G_FLOG10 %0
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$q0 = COPY %1(<2 x s64>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_log10_half
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0:
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liveins: $h0
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; CHECK-LABEL: name: test_log10_half
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; CHECK: [[REG1:%[0-9]+]]:_(s32) = G_FPEXT %0(s16)
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; CHECK-NEXT: ADJCALLSTACKDOWN
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; CHECK-NEXT: $s0 = COPY [[REG1]](s32)
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; CHECK-NEXT: BL &log10
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; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK-NEXT: ADJCALLSTACKUP
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; CHECK-NEXT: [[RES:%[0-9]+]]:_(s16) = G_FPTRUNC [[REG2]](s32)
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%0:_(s16) = COPY $h0
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%1:_(s16) = G_FLOG10 %0
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$h0 = COPY %1(s16)
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RET_ReallyLR implicit $h0
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@ -268,7 +268,7 @@
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# DEBUG: .. type index coverage check SKIPPED: no rules defined
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#
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# DEBUG-NEXT: G_FLOG10 (opcode {{[0-9]+}}): 1 type index
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# DEBUG: .. type index coverage check SKIPPED: no rules defined
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# DEBUG: .. the first uncovered type index: 1, OK
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#
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# DEBUG-NEXT: G_FNEG (opcode {{[0-9]+}}): 1 type index
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# DEBUG: .. the first uncovered type index: 1, OK
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@ -80,10 +80,14 @@ define %v4f16 @test_v4f16.log(%v4f16 %a) {
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%1 = call %v4f16 @llvm.log.v4f16(%v4f16 %a)
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ret %v4f16 %1
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}
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; FALLBACK-NOT: remark{{.*}}test_v4f16.log10
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define %v4f16 @test_v4f16.log10(%v4f16 %a) {
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; This operation is expanded, whether with or without +fullfp16.
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; CHECK-LABEL: test_v4f16.log10:
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; CHECK-COUNT-4: bl log10
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; GISEL-LABEL: test_v4f16.log10:
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; GISEL-COUNT-4: bl log10
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%1 = call %v4f16 @llvm.log10.v4f16(%v4f16 %a)
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ret %v4f16 %1
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}
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@ -251,10 +255,14 @@ define %v8f16 @test_v8f16.log(%v8f16 %a) {
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%1 = call %v8f16 @llvm.log.v8f16(%v8f16 %a)
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ret %v8f16 %1
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}
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; FALLBACK-NOT: remark{{.*}}test_v8f16.log10
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define %v8f16 @test_v8f16.log10(%v8f16 %a) {
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; This operation is expanded, whether with or without +fullfp16.
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; CHECK-LABEL: test_v8f16.log10:
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; CHECK-COUNT-8: bl log10
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; GISEL-LABEL: test_v8f16.log10:
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; GISEL-COUNT-8: bl log10
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%1 = call %v8f16 @llvm.log10.v8f16(%v8f16 %a)
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ret %v8f16 %1
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}
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@ -410,9 +418,13 @@ define %v2f32 @test_v2f32.log(%v2f32 %a) {
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%1 = call %v2f32 @llvm.log.v2f32(%v2f32 %a)
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ret %v2f32 %1
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}
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; FALLBACK-NOT: remark{{.*}}test_v2f32.log10
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; CHECK: test_v2f32.log10:
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; GISEL: test_v2f32.log10:
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define %v2f32 @test_v2f32.log10(%v2f32 %a) {
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; CHECK: log
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; GISEL: log
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%1 = call %v2f32 @llvm.log10.v2f32(%v2f32 %a)
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ret %v2f32 %1
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}
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@ -544,9 +556,12 @@ define %v4f32 @test_v4f32.log(%v4f32 %a) {
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%1 = call %v4f32 @llvm.log.v4f32(%v4f32 %a)
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ret %v4f32 %1
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}
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; FALLBACK-NOT: remark{{.*}}test_v4f32.log10
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; CHECK: test_v4f32.log10:
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define %v4f32 @test_v4f32.log10(%v4f32 %a) {
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; CHECK: log
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; GISEL: log
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%1 = call %v4f32 @llvm.log10.v4f32(%v4f32 %a)
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ret %v4f32 %1
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}
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@ -677,9 +692,13 @@ define %v2f64 @test_v2f64.log(%v2f64 %a) {
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%1 = call %v2f64 @llvm.log.v2f64(%v2f64 %a)
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ret %v2f64 %1
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}
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; FALLBACK-NOT: remark{{.*}}test_v2f64.log10
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; CHECK: test_v2f64.log10:
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; GISEL: test_v2f64.log10:
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define %v2f64 @test_v2f64.log10(%v2f64 %a) {
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; CHECK: log
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; GISEL: log
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%1 = call %v2f64 @llvm.log10.v2f64(%v2f64 %a)
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ret %v2f64 %1
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}
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@ -912,6 +912,9 @@ define half @test_log(half %a) #0 {
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ret half %r
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}
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; FALLBACK-NOT: remark:{{.*}}test_log10
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; FALLBACK-FP16-NOT: remark:{{.*}}test_log10
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; CHECK-COMMON-LABEL: test_log10:
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; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]!
|
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; CHECK-COMMON-NEXT: mov x29, sp
|
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|
|
@ -920,6 +923,16 @@ define half @test_log(half %a) #0 {
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; CHECK-COMMON-NEXT: fcvt h0, s0
|
||||
; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #16
|
||||
; CHECK-COMMON-NEXT: ret
|
||||
|
||||
; GISEL-LABEL: test_log10:
|
||||
; GISEL-NEXT: stp x29, x30, [sp, #-16]!
|
||||
; GISEL-NEXT: mov x29, sp
|
||||
; GISEL-NEXT: fcvt s0, h0
|
||||
; GISEL-NEXT: bl {{_?}}log10f
|
||||
; GISEL-NEXT: fcvt h0, s0
|
||||
; GISEL-NEXT: ldp x29, x30, [sp], #16
|
||||
; GISEL-NEXT: ret
|
||||
|
||||
define half @test_log10(half %a) #0 {
|
||||
%r = call half @llvm.log10.f16(half %a)
|
||||
ret half %r
|
||||
|
|
|
|||
Loading…
Reference in New Issue