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R600/SI: Add generic pseudo SMRD instructions 

llvm-svn: 218765
This commit is contained in:
Tom Stellard 2014-10-01 14:44:42 +00:00
parent d90c20bc26
commit c470c96e6b
2 changed files with 39 additions and 14 deletions
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4
llvm/lib/Target/R600/SIInstrFormats.td
View File

@ -206,8 +206,8 @@ class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> :
let UseNamedOperandTable = 1; let UseNamedOperandTable = 1;
} }
class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm, class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
list<dag> pattern> : InstSI<outs, ins, asm, pattern>, SMRDe<op, imm> { InstSI<outs, ins, asm, pattern> {
let LGKM_CNT = 1; let LGKM_CNT = 1;
let SMRD = 1; let SMRD = 1;

49
llvm/lib/Target/R600/SIInstrInfo.td
View File

@ -250,6 +250,11 @@ def DSTOMOD {
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class SIMCInstr <string pseudo, int subtarget> {
string PseudoInstr = pseudo;
int Subtarget = subtarget;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Scalar classes // Scalar classes
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@ -307,18 +312,43 @@ class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK <
opName#" $dst, $src0", pattern opName#" $dst, $src0", pattern
>; >;
multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass baseClass, //===----------------------------------------------------------------------===//
// SMRD classes
//===----------------------------------------------------------------------===//
class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
SMRD <outs, ins, "", pattern>,
SIMCInstr<opName, SISubtarget.NONE> {
let isPseudo = 1;
}
class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
string asm> :
SMRD <outs, ins, asm, []>,
SMRDe <op, imm>,
SIMCInstr<opName, SISubtarget.SI>;
multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
string asm, list<dag> pattern> {
def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
}
multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
RegisterClass dstClass> { RegisterClass dstClass> {
def _IMM : SMRD < defm _IMM : SMRD_m <
op, 1, (outs dstClass:$dst), op, opName#"_IMM", 1, (outs dstClass:$dst),
(ins baseClass:$sbase, u32imm:$offset), (ins baseClass:$sbase, u32imm:$offset),
asm#" $dst, $sbase, $offset", [] opName#" $dst, $sbase, $offset", []
>; >;
def _SGPR : SMRD < defm _SGPR : SMRD_m <
op, 0, (outs dstClass:$dst), op, opName#"_SGPR", 0, (outs dstClass:$dst),
(ins baseClass:$sbase, SReg_32:$soff), (ins baseClass:$sbase, SReg_32:$soff),
asm#" $dst, $sbase, $soff", [] opName#" $dst, $sbase, $soff", []
>; >;
} }
@ -531,11 +561,6 @@ class AtomicNoRet <string noRetOp, bit isRet> {
bit IsRet = isRet; bit IsRet = isRet;
} }
class SIMCInstr <string pseudo, int subtarget> {
string PseudoInstr = pseudo;
int Subtarget = subtarget;
}
class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> { class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
bits<2> src0_modifiers = !if(HasModifiers, ?, 0); bits<2> src0_modifiers = !if(HasModifiers, ?, 0);