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[AArch64][SVE] Asm: Replace 'IsVector' by 'RegKind' in AArch64AsmParser (NFC) 

Patch [2/5] in a series to add assembler/disassembler support for AArch64 SVE unpredicated ADD/SUB instructions.

This change is a non functional change that adds RegKind as an alternative to 'isVector' to prepare it for newer types (SVE data vectors and predicate vectors) that will be added in next patches (where the SVE data vector is added as part of this patch set)

Patch by Sander De Smalen.

Reviewed by: rengolin

Differential Revision: https://reviews.llvm.org/D39088

llvm-svn: 317569
This commit is contained in:
Florian Hahn 2017-11-07 13:07:50 +00:00
parent 178818ba20
commit c4422247b3
2 changed files with 69 additions and 46 deletions
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9
llvm/lib/Target/AArch64/AArch64RegisterInfo.td
View File

@ -460,11 +460,11 @@ def QQQQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqQuads)> {
// assmebler matching. // assmebler matching.
def VectorReg64AsmOperand : AsmOperandClass { def VectorReg64AsmOperand : AsmOperandClass {
let Name = "VectorReg64"; let Name = "VectorReg64";
let PredicateMethod = "isVectorReg"; let PredicateMethod = "isNeonVectorReg";
} }
def VectorReg128AsmOperand : AsmOperandClass { def VectorReg128AsmOperand : AsmOperandClass {
let Name = "VectorReg128"; let Name = "VectorReg128";
let PredicateMethod = "isVectorReg"; let PredicateMethod = "isNeonVectorReg";
} }
def V64 : RegisterOperand<FPR64, "printVRegOperand"> { def V64 : RegisterOperand<FPR64, "printVRegOperand"> {
@ -475,7 +475,10 @@ def V128 : RegisterOperand<FPR128, "printVRegOperand"> {
let ParserMatchClass = VectorReg128AsmOperand; let ParserMatchClass = VectorReg128AsmOperand;
} }
def VectorRegLoAsmOperand : AsmOperandClass { let Name = "VectorRegLo"; } def VectorRegLoAsmOperand : AsmOperandClass {
let Name = "VectorRegLo";
let PredicateMethod = "isNeonVectorRegLo";
}
def V128_lo : RegisterOperand<FPR128_lo, "printVRegOperand"> { def V128_lo : RegisterOperand<FPR128_lo, "printVRegOperand"> {
let ParserMatchClass = VectorRegLoAsmOperand; let ParserMatchClass = VectorRegLoAsmOperand;
} }

106
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
View File

@ -59,12 +59,14 @@ using namespace llvm;
namespace { namespace {
enum class RegKind {Scalar, NeonVector};
class AArch64AsmParser : public MCTargetAsmParser { class AArch64AsmParser : public MCTargetAsmParser {
private: private:
StringRef Mnemonic; ///< Instruction mnemonic. StringRef Mnemonic; ///< Instruction mnemonic.
// Map of register aliases registers via the .req directive. // Map of register aliases registers via the .req directive.
StringMap<std::pair<bool, unsigned>> RegisterReqs; StringMap<std::pair<RegKind, unsigned>> RegisterReqs;
AArch64TargetStreamer &getTargetStreamer() { AArch64TargetStreamer &getTargetStreamer() {
MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
@ -77,7 +79,7 @@ private:
void createSysAlias(uint16_t Encoding, OperandVector &Operands, SMLoc S); void createSysAlias(uint16_t Encoding, OperandVector &Operands, SMLoc S);
AArch64CC::CondCode parseCondCodeString(StringRef Cond); AArch64CC::CondCode parseCondCodeString(StringRef Cond);
bool parseCondCode(OperandVector &Operands, bool invertCondCode); bool parseCondCode(OperandVector &Operands, bool invertCondCode);
unsigned matchRegisterNameAlias(StringRef Name, bool isVector); unsigned matchRegisterNameAlias(StringRef Name, RegKind Kind);
int tryParseRegister(); int tryParseRegister();
int tryMatchVectorRegister(StringRef &Kind, bool expected); int tryMatchVectorRegister(StringRef &Kind, bool expected);
bool parseRegister(OperandVector &Operands); bool parseRegister(OperandVector &Operands);
@ -126,7 +128,7 @@ private:
OperandMatchResultTy tryParseFPImm(OperandVector &Operands); OperandMatchResultTy tryParseFPImm(OperandVector &Operands);
OperandMatchResultTy tryParseAddSubImm(OperandVector &Operands); OperandMatchResultTy tryParseAddSubImm(OperandVector &Operands);
OperandMatchResultTy tryParseGPR64sp0Operand(OperandVector &Operands); OperandMatchResultTy tryParseGPR64sp0Operand(OperandVector &Operands);
bool tryParseVectorRegister(OperandVector &Operands); bool tryParseNeonVectorRegister(OperandVector &Operands);
OperandMatchResultTy tryParseGPRSeqPair(OperandVector &Operands); OperandMatchResultTy tryParseGPRSeqPair(OperandVector &Operands);
public: public:
@ -194,7 +196,7 @@ private:
struct RegOp { struct RegOp {
unsigned RegNum; unsigned RegNum;
bool isVector; RegKind Kind;
}; };
struct VectorListOp { struct VectorListOp {
@ -804,34 +806,39 @@ public:
return SysReg.PStateField != -1U; return SysReg.PStateField != -1U;
} }
bool isReg() const override { return Kind == k_Register && !Reg.isVector; } bool isReg() const override {
bool isVectorReg() const { return Kind == k_Register && Reg.isVector; } return Kind == k_Register && Reg.Kind == RegKind::Scalar;
}
bool isVectorRegLo() const { bool isNeonVectorReg() const {
return Kind == k_Register && Reg.isVector && return Kind == k_Register && Reg.Kind == RegKind::NeonVector;
}
bool isNeonVectorRegLo() const {
return Kind == k_Register && Reg.Kind == RegKind::NeonVector &&
AArch64MCRegisterClasses[AArch64::FPR128_loRegClassID].contains( AArch64MCRegisterClasses[AArch64::FPR128_loRegClassID].contains(
Reg.RegNum); Reg.RegNum);
} }
bool isGPR32as64() const { bool isGPR32as64() const {
return Kind == k_Register && !Reg.isVector && return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum); AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum);
} }
bool isWSeqPair() const { bool isWSeqPair() const {
return Kind == k_Register && !Reg.isVector && return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
AArch64MCRegisterClasses[AArch64::WSeqPairsClassRegClassID].contains( AArch64MCRegisterClasses[AArch64::WSeqPairsClassRegClassID].contains(
Reg.RegNum); Reg.RegNum);
} }
bool isXSeqPair() const { bool isXSeqPair() const {
return Kind == k_Register && !Reg.isVector && return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
AArch64MCRegisterClasses[AArch64::XSeqPairsClassRegClassID].contains( AArch64MCRegisterClasses[AArch64::XSeqPairsClassRegClassID].contains(
Reg.RegNum); Reg.RegNum);
} }
bool isGPR64sp0() const { bool isGPR64sp0() const {
return Kind == k_Register && !Reg.isVector && return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].contains(Reg.RegNum); AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].contains(Reg.RegNum);
} }
@ -1564,10 +1571,10 @@ public:
} }
static std::unique_ptr<AArch64Operand> static std::unique_ptr<AArch64Operand>
CreateReg(unsigned RegNum, bool isVector, SMLoc S, SMLoc E, MCContext &Ctx) { CreateReg(unsigned RegNum, RegKind Kind, SMLoc S, SMLoc E, MCContext &Ctx) {
auto Op = make_unique<AArch64Operand>(k_Register, Ctx); auto Op = make_unique<AArch64Operand>(k_Register, Ctx);
Op->Reg.RegNum = RegNum; Op->Reg.RegNum = RegNum;
Op->Reg.isVector = isVector; Op->Reg.Kind = Kind;
Op->StartLoc = S; Op->StartLoc = S;
Op->EndLoc = E; Op->EndLoc = E;
return Op; return Op;
@ -1791,7 +1798,7 @@ static unsigned MatchRegisterName(StringRef Name);
/// } /// }
static unsigned matchVectorRegName(StringRef Name) { static unsigned MatchNeonVectorRegName(StringRef Name) {
return StringSwitch<unsigned>(Name.lower()) return StringSwitch<unsigned>(Name.lower())
.Case("v0", AArch64::Q0) .Case("v0", AArch64::Q0)
.Case("v1", AArch64::Q1) .Case("v1", AArch64::Q1)
@ -1881,19 +1888,27 @@ bool AArch64AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
// Matches a register name or register alias previously defined by '.req' // Matches a register name or register alias previously defined by '.req'
unsigned AArch64AsmParser::matchRegisterNameAlias(StringRef Name, unsigned AArch64AsmParser::matchRegisterNameAlias(StringRef Name,
bool isVector) { RegKind Kind) {
unsigned RegNum = isVector ? matchVectorRegName(Name) unsigned RegNum;
: MatchRegisterName(Name); switch (Kind) {
case RegKind::Scalar:
RegNum = MatchRegisterName(Name);
break;
case RegKind::NeonVector:
RegNum = MatchNeonVectorRegName(Name);
break;
}
if (RegNum == 0) { if (!RegNum) {
// Check for aliases registered via .req. Canonicalize to lower case. // Check for aliases registered via .req. Canonicalize to lower case.
// That's more consistent since register names are case insensitive, and // That's more consistent since register names are case insensitive, and
// it's how the original entry was passed in from MC/MCParser/AsmParser. // it's how the original entry was passed in from MC/MCParser/AsmParser.
auto Entry = RegisterReqs.find(Name.lower()); auto Entry = RegisterReqs.find(Name.lower());
if (Entry == RegisterReqs.end()) if (Entry == RegisterReqs.end())
return 0; return 0;
// set RegNum if the match is the right kind of register // set RegNum if the match is the right kind of register
if (isVector == Entry->getValue().first) if (Kind == Entry->getValue().first)
RegNum = Entry->getValue().second; RegNum = Entry->getValue().second;
} }
return RegNum; return RegNum;
@ -1909,7 +1924,7 @@ int AArch64AsmParser::tryParseRegister() {
return -1; return -1;
std::string lowerCase = Tok.getString().lower(); std::string lowerCase = Tok.getString().lower();
unsigned RegNum = matchRegisterNameAlias(lowerCase, false); unsigned RegNum = matchRegisterNameAlias(lowerCase, RegKind::Scalar);
// Also handle a few aliases of registers. // Also handle a few aliases of registers.
if (RegNum == 0) if (RegNum == 0)
RegNum = StringSwitch<unsigned>(lowerCase) RegNum = StringSwitch<unsigned>(lowerCase)
@ -1940,7 +1955,7 @@ int AArch64AsmParser::tryMatchVectorRegister(StringRef &Kind, bool expected) {
// a '.'. // a '.'.
size_t Start = 0, Next = Name.find('.'); size_t Start = 0, Next = Name.find('.');
StringRef Head = Name.slice(Start, Next); StringRef Head = Name.slice(Start, Next);
unsigned RegNum = matchRegisterNameAlias(Head, true); unsigned RegNum = matchRegisterNameAlias(Head, RegKind::NeonVector);
if (RegNum) { if (RegNum) {
if (Next != StringRef::npos) { if (Next != StringRef::npos) {
@ -2559,8 +2574,8 @@ AArch64AsmParser::tryParseSysReg(OperandVector &Operands) {
return MatchOperand_Success; return MatchOperand_Success;
} }
/// tryParseVectorRegister - Parse a vector register operand. /// tryParseNeonVectorRegister - Parse a vector register operand.
bool AArch64AsmParser::tryParseVectorRegister(OperandVector &Operands) { bool AArch64AsmParser::tryParseNeonVectorRegister(OperandVector &Operands) {
MCAsmParser &Parser = getParser(); MCAsmParser &Parser = getParser();
if (Parser.getTok().isNot(AsmToken::Identifier)) if (Parser.getTok().isNot(AsmToken::Identifier))
return true; return true;
@ -2572,7 +2587,9 @@ bool AArch64AsmParser::tryParseVectorRegister(OperandVector &Operands) {
if (Reg == -1) if (Reg == -1)
return true; return true;
Operands.push_back( Operands.push_back(
AArch64Operand::CreateReg(Reg, true, S, getLoc(), getContext())); AArch64Operand::CreateReg(Reg, RegKind::NeonVector, S, getLoc(),
getContext()));
// If there was an explicit qualifier, that goes on as a literal text // If there was an explicit qualifier, that goes on as a literal text
// operand. // operand.
if (!Kind.empty()) if (!Kind.empty())
@ -2606,16 +2623,16 @@ bool AArch64AsmParser::tryParseVectorRegister(OperandVector &Operands) {
/// parseRegister - Parse a non-vector register operand. /// parseRegister - Parse a non-vector register operand.
bool AArch64AsmParser::parseRegister(OperandVector &Operands) { bool AArch64AsmParser::parseRegister(OperandVector &Operands) {
SMLoc S = getLoc(); SMLoc S = getLoc();
// Try for a vector register. // Try for a vector (neon) register.
if (!tryParseVectorRegister(Operands)) if (!tryParseNeonVectorRegister(Operands))
return false; return false;
// Try for a scalar register. // Try for a scalar register.
int64_t Reg = tryParseRegister(); int64_t Reg = tryParseRegister();
if (Reg == -1) if (Reg == -1)
return true; return true;
Operands.push_back( Operands.push_back(AArch64Operand::CreateReg(Reg, RegKind::Scalar, S,
AArch64Operand::CreateReg(Reg, false, S, getLoc(), getContext())); getLoc(), getContext()));
return false; return false;
} }
@ -2783,7 +2800,7 @@ AArch64AsmParser::tryParseGPR64sp0Operand(OperandVector &Operands) {
if (!Tok.is(AsmToken::Identifier)) if (!Tok.is(AsmToken::Identifier))
return MatchOperand_NoMatch; return MatchOperand_NoMatch;
unsigned RegNum = matchRegisterNameAlias(Tok.getString().lower(), false); unsigned RegNum = matchRegisterNameAlias(Tok.getString().lower(), RegKind::Scalar);
MCContext &Ctx = getContext(); MCContext &Ctx = getContext();
const MCRegisterInfo *RI = Ctx.getRegisterInfo(); const MCRegisterInfo *RI = Ctx.getRegisterInfo();
@ -2795,7 +2812,7 @@ AArch64AsmParser::tryParseGPR64sp0Operand(OperandVector &Operands) {
if (!parseOptionalToken(AsmToken::Comma)) { if (!parseOptionalToken(AsmToken::Comma)) {
Operands.push_back( Operands.push_back(
AArch64Operand::CreateReg(RegNum, false, S, getLoc(), Ctx)); AArch64Operand::CreateReg(RegNum, RegKind::Scalar, S, getLoc(), Ctx));
return MatchOperand_Success; return MatchOperand_Success;
} }
@ -2814,7 +2831,7 @@ AArch64AsmParser::tryParseGPR64sp0Operand(OperandVector &Operands) {
} }
Operands.push_back( Operands.push_back(
AArch64Operand::CreateReg(RegNum, false, S, getLoc(), Ctx)); AArch64Operand::CreateReg(RegNum, RegKind::Scalar, S, getLoc(), Ctx));
return MatchOperand_Success; return MatchOperand_Success;
} }
@ -3529,8 +3546,8 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
Operands[0] = AArch64Operand::CreateToken( Operands[0] = AArch64Operand::CreateToken(
"bfm", false, Op.getStartLoc(), getContext()); "bfm", false, Op.getStartLoc(), getContext());
Operands[2] = AArch64Operand::CreateReg( Operands[2] = AArch64Operand::CreateReg(
RegWidth == 32 ? AArch64::WZR : AArch64::XZR, false, SMLoc(), RegWidth == 32 ? AArch64::WZR : AArch64::XZR, RegKind::Scalar,
SMLoc(), getContext()); SMLoc(), SMLoc(), getContext());
Operands[3] = AArch64Operand::CreateImm( Operands[3] = AArch64Operand::CreateImm(
ImmRExpr, LSBOp.getStartLoc(), LSBOp.getEndLoc(), getContext()); ImmRExpr, LSBOp.getStartLoc(), LSBOp.getEndLoc(), getContext());
Operands.emplace_back( Operands.emplace_back(
@ -3666,8 +3683,9 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
AArch64Operand &Op = static_cast<AArch64Operand &>(*Operands[2]); AArch64Operand &Op = static_cast<AArch64Operand &>(*Operands[2]);
if (Op.isReg()) { if (Op.isReg()) {
unsigned Reg = getXRegFromWReg(Op.getReg()); unsigned Reg = getXRegFromWReg(Op.getReg());
Operands[2] = AArch64Operand::CreateReg(Reg, false, Op.getStartLoc(), Operands[2] = AArch64Operand::CreateReg(Reg, RegKind::Scalar,
Op.getEndLoc(), getContext()); Op.getStartLoc(), Op.getEndLoc(),
getContext());
} }
} }
// FIXME: Likewise for sxt[bh] with a Xd dst operand // FIXME: Likewise for sxt[bh] with a Xd dst operand
@ -3681,7 +3699,8 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
AArch64Operand &Op = static_cast<AArch64Operand &>(*Operands[2]); AArch64Operand &Op = static_cast<AArch64Operand &>(*Operands[2]);
if (Op.isReg()) { if (Op.isReg()) {
unsigned Reg = getXRegFromWReg(Op.getReg()); unsigned Reg = getXRegFromWReg(Op.getReg());
Operands[2] = AArch64Operand::CreateReg(Reg, false, Op.getStartLoc(), Operands[2] = AArch64Operand::CreateReg(Reg, RegKind::Scalar,
Op.getStartLoc(),
Op.getEndLoc(), getContext()); Op.getEndLoc(), getContext());
} }
} }
@ -3697,7 +3716,8 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
AArch64Operand &Op = static_cast<AArch64Operand &>(*Operands[1]); AArch64Operand &Op = static_cast<AArch64Operand &>(*Operands[1]);
if (Op.isReg()) { if (Op.isReg()) {
unsigned Reg = getWRegFromXReg(Op.getReg()); unsigned Reg = getWRegFromXReg(Op.getReg());
Operands[1] = AArch64Operand::CreateReg(Reg, false, Op.getStartLoc(), Operands[1] = AArch64Operand::CreateReg(Reg, RegKind::Scalar,
Op.getStartLoc(),
Op.getEndLoc(), getContext()); Op.getEndLoc(), getContext());
} }
} }
@ -4158,14 +4178,14 @@ bool AArch64AsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
Parser.Lex(); // Eat the '.req' token. Parser.Lex(); // Eat the '.req' token.
SMLoc SRegLoc = getLoc(); SMLoc SRegLoc = getLoc();
unsigned RegNum = tryParseRegister(); unsigned RegNum = tryParseRegister();
bool IsVector = false; RegKind RegisterKind = RegKind::Scalar;
if (RegNum == static_cast<unsigned>(-1)) { if (RegNum == static_cast<unsigned>(-1)) {
StringRef Kind; StringRef Kind;
RegisterKind = RegKind::NeonVector;
RegNum = tryMatchVectorRegister(Kind, false); RegNum = tryMatchVectorRegister(Kind, false);
if (!Kind.empty()) if (!Kind.empty())
return Error(SRegLoc, "vector register without type specifier expected"); return Error(SRegLoc, "vector register without type specifier expected");
IsVector = true;
} }
if (RegNum == static_cast<unsigned>(-1)) if (RegNum == static_cast<unsigned>(-1))
@ -4176,7 +4196,7 @@ bool AArch64AsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
"unexpected input in .req directive")) "unexpected input in .req directive"))
return true; return true;
auto pair = std::make_pair(IsVector, RegNum); auto pair = std::make_pair(RegisterKind, RegNum);
if (RegisterReqs.insert(std::make_pair(Name, pair)).first->second != pair) if (RegisterReqs.insert(std::make_pair(Name, pair)).first->second != pair)
Warning(L, "ignoring redefinition of register alias '" + Name + "'"); Warning(L, "ignoring redefinition of register alias '" + Name + "'");
@ -4388,8 +4408,8 @@ AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) {
&AArch64MCRegisterClasses[AArch64::WSeqPairsClassRegClassID]); &AArch64MCRegisterClasses[AArch64::WSeqPairsClassRegClassID]);
} }
Operands.push_back(AArch64Operand::CreateReg(Pair, false, S, getLoc(), Operands.push_back(AArch64Operand::CreateReg(Pair, RegKind::Scalar, S,
getContext())); getLoc(), getContext()));
return MatchOperand_Success; return MatchOperand_Success;
} }