forked from OSchip/llvm-project
[inline-asm]No error for conflict between inputs\outputs and clobber list
According to extended asm syntax, a case where the clobber list includes a variable from the inputs or outputs should be an error - conflict. for example: const long double a = 0.0; int main() { char b; double t1 = a; __asm__ ("fucompp": "=a" (b) : "u" (t1), "t" (t1) : "cc", "st", "st(1)"); return 0; } This should conflict with the output - t1 which is st, and st which is st aswell. The patch fixes it. Commit on behald of Ziv Izhar. Differential Revision: https://reviews.llvm.org/D15075 llvm-svn: 290539
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600941351e
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c42fd03bf8
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@ -7069,6 +7069,10 @@ let CategoryName = "Inline Assembly Issue" in {
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"constraint '%0' is already present here">;
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}
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def error_inoutput_conflict_with_clobber : Error<
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"asm-specifier for input or output variable conflicts with asm"
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" clobber list">;
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let CategoryName = "Semantic Issue" in {
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def err_invalid_conversion_between_vectors : Error<
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@ -605,8 +605,16 @@ public:
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/// \brief Returns the "normalized" GCC register name.
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///
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/// For example, on x86 it will return "ax" when "eax" is passed in.
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StringRef getNormalizedGCCRegisterName(StringRef Name) const;
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/// ReturnCannonical true will return the register name without any additions
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/// such as "{}" or "%" in it's canonical form, for example:
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/// ReturnCanonical = true and Name = "rax", will return "ax".
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StringRef getNormalizedGCCRegisterName(StringRef Name,
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bool ReturnCanonical = false) const;
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virtual StringRef getConstraintRegister(const StringRef &Constraint,
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const StringRef &Expression) const {
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return "";
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}
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struct ConstraintInfo {
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enum {
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@ -410,8 +410,8 @@ bool TargetInfo::isValidGCCRegisterName(StringRef Name) const {
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return false;
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}
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StringRef
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TargetInfo::getNormalizedGCCRegisterName(StringRef Name) const {
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StringRef TargetInfo::getNormalizedGCCRegisterName(StringRef Name,
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bool ReturnCanonical) const {
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assert(isValidGCCRegisterName(Name) && "Invalid register passed in");
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// Get rid of any register prefix.
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@ -436,7 +436,7 @@ TargetInfo::getNormalizedGCCRegisterName(StringRef Name) const {
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// Make sure the register that the additional name is for is within
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// the bounds of the register names from above.
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if (AN == Name && ARN.RegNum < Names.size())
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return Name;
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return ReturnCanonical ? Names[ARN.RegNum] : Name;
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}
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// Now check aliases.
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@ -2789,6 +2789,40 @@ public:
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const char *getClobbers() const override {
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return "~{dirflag},~{fpsr},~{flags}";
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}
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StringRef getConstraintRegister(const StringRef &Constraint,
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const StringRef &Expression) const override {
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StringRef::iterator I, E;
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for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) {
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if (isalpha(*I))
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break;
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}
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if (I == E)
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return "";
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switch (*I) {
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// For the register constraints, return the matching register name
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case 'a':
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return "ax";
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case 'b':
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return "bx";
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case 'c':
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return "cx";
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case 'd':
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return "dx";
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case 'S':
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return "si";
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case 'D':
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return "di";
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// In case the constraint is 'r' we need to return Expression
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case 'r':
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return Expression;
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default:
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// Default value if there is no constraint for the register
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return "";
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}
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return "";
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}
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void getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const override;
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static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
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@ -1010,40 +1010,33 @@ __readgsqword(unsigned long __offset) {
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#if defined(__i386__) || defined(__x86_64__)
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static __inline__ void __DEFAULT_FN_ATTRS
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__movsb(unsigned char *__dst, unsigned char const *__src, size_t __n) {
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__asm__("rep movsb" : : "D"(__dst), "S"(__src), "c"(__n)
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: "%edi", "%esi", "%ecx");
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__asm__("rep movsb" : : "D"(__dst), "S"(__src), "c"(__n));
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}
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static __inline__ void __DEFAULT_FN_ATTRS
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__movsd(unsigned long *__dst, unsigned long const *__src, size_t __n) {
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__asm__("rep movsl" : : "D"(__dst), "S"(__src), "c"(__n)
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: "%edi", "%esi", "%ecx");
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__asm__("rep movsl" : : "D"(__dst), "S"(__src), "c"(__n));
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}
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static __inline__ void __DEFAULT_FN_ATTRS
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__movsw(unsigned short *__dst, unsigned short const *__src, size_t __n) {
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__asm__("rep movsw" : : "D"(__dst), "S"(__src), "c"(__n)
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: "%edi", "%esi", "%ecx");
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__asm__("rep movsw" : : "D"(__dst), "S"(__src), "c"(__n));
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}
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static __inline__ void __DEFAULT_FN_ATTRS
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__stosd(unsigned long *__dst, unsigned long __x, size_t __n) {
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__asm__("rep stosl" : : "D"(__dst), "a"(__x), "c"(__n)
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: "%edi", "%ecx");
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__asm__("rep stosl" : : "D"(__dst), "a"(__x), "c"(__n));
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}
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static __inline__ void __DEFAULT_FN_ATTRS
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__stosw(unsigned short *__dst, unsigned short __x, size_t __n) {
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__asm__("rep stosw" : : "D"(__dst), "a"(__x), "c"(__n)
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: "%edi", "%ecx");
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__asm__("rep stosw" : : "D"(__dst), "a"(__x), "c"(__n));
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}
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#endif
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#ifdef __x86_64__
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static __inline__ void __DEFAULT_FN_ATTRS
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__movsq(unsigned long long *__dst, unsigned long long const *__src, size_t __n) {
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__asm__("rep movsq" : : "D"(__dst), "S"(__src), "c"(__n)
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: "%edi", "%esi", "%ecx");
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__asm__("rep movsq" : : "D"(__dst), "S"(__src), "c"(__n));
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}
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static __inline__ void __DEFAULT_FN_ATTRS
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__stosq(unsigned __int64 *__dst, unsigned __int64 __x, size_t __n) {
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__asm__("rep stosq" : : "D"(__dst), "a"(__x), "c"(__n)
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: "%edi", "%ecx");
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__asm__("rep stosq" : : "D"(__dst), "a"(__x), "c"(__n));
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}
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#endif
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@ -22,6 +22,7 @@
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#include "clang/Sema/ScopeInfo.h"
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#include "clang/Sema/SemaInternal.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/StringSet.h"
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#include "llvm/MC/MCParser/MCAsmParser.h"
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using namespace clang;
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using namespace sema;
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@ -137,6 +138,57 @@ static bool checkExprMemoryConstraintCompat(Sema &S, Expr *E,
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return false;
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}
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// Extracting the register name from the Expression value,
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// if there is no register name to extract, returns ""
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static StringRef extractRegisterName(const Expr *Expression,
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const TargetInfo &Target) {
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Expression = Expression->IgnoreImpCasts();
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if (const DeclRefExpr *AsmDeclRef = dyn_cast<DeclRefExpr>(Expression)) {
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// Handle cases where the expression is a variable
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const VarDecl *Variable = dyn_cast<VarDecl>(AsmDeclRef->getDecl());
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if (Variable && Variable->getStorageClass() == SC_Register) {
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if (AsmLabelAttr *Attr = Variable->getAttr<AsmLabelAttr>())
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if (Target.isValidGCCRegisterName(Attr->getLabel()))
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return Target.getNormalizedGCCRegisterName(Attr->getLabel(), true);
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}
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}
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return "";
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}
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// Checks if there is a conflict between the input and output lists with the
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// clobbers list. If there's a conflict, returns the location of the
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// conflicted clobber, else returns nullptr
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static SourceLocation
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getClobberConflictLocation(MultiExprArg Exprs, StringLiteral **Constraints,
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StringLiteral **Clobbers, int NumClobbers,
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const TargetInfo &Target, ASTContext &Cont) {
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llvm::StringSet<> InOutVars;
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// Collect all the input and output registers from the extended asm
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// statement
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// in order to check for conflicts with the clobber list
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for (int i = 0; i < Exprs.size(); ++i) {
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StringRef Constraint = Constraints[i]->getString();
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StringRef InOutReg = Target.getConstraintRegister(
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Constraint, extractRegisterName(Exprs[i], Target));
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if (InOutReg != "")
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InOutVars.insert(InOutReg);
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}
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// Check for each item in the clobber list if it conflicts with the input
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// or output
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for (int i = 0; i < NumClobbers; ++i) {
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StringRef Clobber = Clobbers[i]->getString();
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// We only check registers, therefore we don't check cc and memory
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// clobbers
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if (Clobber == "cc" || Clobber == "memory")
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continue;
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Clobber = Target.getNormalizedGCCRegisterName(Clobber, true);
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// Go over the output's registers we collected
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if (InOutVars.count(Clobber))
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return Clobbers[i]->getLocStart();
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}
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return SourceLocation();
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}
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StmtResult Sema::ActOnGCCAsmStmt(SourceLocation AsmLoc, bool IsSimple,
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bool IsVolatile, unsigned NumOutputs,
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unsigned NumInputs, IdentifierInfo **Names,
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return StmtError();
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}
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// Check for conflicts between clobber list and input or output lists
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SourceLocation ConstraintLoc =
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getClobberConflictLocation(Exprs, Constraints, Clobbers, NumClobbers,
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Context.getTargetInfo(), Context);
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if (ConstraintLoc.isValid())
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return Diag(ConstraintLoc, diag::error_inoutput_conflict_with_clobber);
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return NS;
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}
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@ -28,6 +28,16 @@ void clobbers() {
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asm ("nop" : : : "204"); // expected-error {{unknown register name '204' in asm}}
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asm ("nop" : : : "-1"); // expected-error {{unknown register name '-1' in asm}}
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asm ("nop" : : : "+1"); // expected-error {{unknown register name '+1' in asm}}
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register void *clobber_conflict asm ("%rcx");
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register void *no_clobber_conflict asm ("%rax");
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int a,b,c;
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asm ("nop" : "=r" (no_clobber_conflict) : "r" (clobber_conflict) : "%rcx"); // expected-error {{asm-specifier for input or output variable conflicts with asm clobber list}}
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asm ("nop" : "=r" (clobber_conflict) : "r" (no_clobber_conflict) : "%rcx"); // expected-error {{asm-specifier for input or output variable conflicts with asm clobber list}}
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asm ("nop" : "=r" (clobber_conflict) : "r" (clobber_conflict) : "%rcx"); // expected-error {{asm-specifier for input or output variable conflicts with asm clobber list}}
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asm ("nop" : "=c" (a) : "r" (no_clobber_conflict) : "%rcx"); // expected-error {{asm-specifier for input or output variable conflicts with asm clobber list}}
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asm ("nop" : "=r" (no_clobber_conflict) : "c" (c) : "%rcx"); // expected-error {{asm-specifier for input or output variable conflicts with asm clobber list}}
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asm ("nop" : "=r" (clobber_conflict) : "c" (c) : "%rcx"); // expected-error {{asm-specifier for input or output variable conflicts with asm clobber list}}
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asm ("nop" : "=a" (a) : "b" (b) : "%rcx", "%rbx"); // expected-error {{asm-specifier for input or output variable conflicts with asm clobber list}}
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}
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// rdar://6094010
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