forked from OSchip/llvm-project
[Clang] Add option to handle behaviour of vector bool/vector pixel.
Added the option `-altivec-src-compat=[mixed,gcc,xl]`. The default at this time is `mixed`. The default behavior for clang is for all vector compares to return a scalar unless the vectors being compared are vector bool or vector pixel. In that case the compare returns a vector. With the gcc case all vector compares return vectors and in the xl case all vector compares return scalars. This patch does not change the default behavior of clang. This option will be used in future patches to implement behaviour compatibility for the vector bool/pixel types. Reviewed By: bmahjour Differential Revision: https://reviews.llvm.org/D103615
This commit is contained in:
Stefan Pintilie
parent
cccc7e5aa8
commit
c3fe847f9d
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@ -7441,6 +7441,12 @@ def warn_deprecated_volatile_structured_binding : Warning<
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"volatile qualifier in structured binding declaration is deprecated">,
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InGroup<DeprecatedVolatile>;
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def warn_deprecated_altivec_src_compat : Warning<
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"Current handling of vector bool and vector pixel types in this context are "
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"deprecated. The default behaviour will soon change to that implied by the "
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"'-altivec-compat=xl' option">,
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InGroup<DiagGroup<"deprecated-altivec-src-compat">>;
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def err_catch_incomplete_ptr : Error<
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"cannot catch pointer to incomplete type %0">;
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def err_catch_incomplete_ref : Error<
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@ -126,6 +126,8 @@ LANGOPT(WritableStrings , 1, 0, "writable string support")
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LANGOPT(ConstStrings , 1, 0, "const-qualified string support")
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ENUM_LANGOPT(LaxVectorConversions, LaxVectorConversionKind, 2,
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LaxVectorConversionKind::All, "lax vector conversions")
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ENUM_LANGOPT(AltivecSrcCompat, AltivecSrcCompatKind, 2,
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AltivecSrcCompatKind::Default, "Altivec source compatibility")
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LANGOPT(ConvergentFunctions, 1, 1, "Assume convergent functions")
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LANGOPT(AltiVec , 1, 0, "AltiVec-style vector initializers")
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LANGOPT(ZVector , 1, 0, "System z vector extensions")
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@ -244,6 +244,18 @@ public:
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All,
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};
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enum class AltivecSrcCompatKind {
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// All vector compares produce scalars except vector pixel and vector bool.
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// The types vector pixel and vector bool return vector results.
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Mixed,
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// All vector compares produce vector results as in GCC.
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GCC,
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// All vector compares produce scalars as in XL.
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XL,
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// Default clang behaviour.
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Default = Mixed,
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};
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enum class SignReturnAddressScopeKind {
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/// No signing for any function.
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None,
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@ -3823,6 +3823,18 @@ def u : JoinedOrSeparate<["-"], "u">, Group<u_Group>;
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def v : Flag<["-"], "v">, Flags<[CC1Option, CoreOption]>,
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HelpText<"Show commands to run and use verbose output">,
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MarshallingInfoFlag<HeaderSearchOpts<"Verbose">>;
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def altivec_src_compat : Joined<["-"], "faltivec-src-compat=">,
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Flags<[CC1Option]>, Group<f_Group>,
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HelpText<"Source-level compatibility for Altivec vectors (for PowerPC "
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"targets). This includes results of vector comparison (scalar for "
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"'xl', vector for 'gcc') as well as behavior when initializing with "
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"a scalar (splatting for 'xl', element zero only for 'gcc'). For "
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"'mixed', the compatibility is as 'gcc' for 'vector bool/vector "
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"pixel' and as 'xl' for other types. Current default is 'mixed'.">,
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Values<"mixed,gcc,xl">,
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NormalizedValuesScope<"LangOptions::AltivecSrcCompatKind">,
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NormalizedValues<["Mixed", "GCC", "XL"]>,
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MarshallingInfoEnum<LangOpts<"AltivecSrcCompat">, "Mixed">;
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def verify_debug_info : Flag<["--"], "verify-debug-info">, Flags<[NoXarchOption]>,
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HelpText<"Verify the binary representation of debug output">;
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def weak_l : Joined<["-"], "weak-l">, Flags<[LinkerInput]>;
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@ -5816,6 +5816,7 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
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(Args.hasArg(options::OPT_mkernel) && types::isCXX(InputType)))
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CmdArgs.push_back("-fapple-kext");
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Args.AddLastArg(CmdArgs, options::OPT_altivec_src_compat);
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Args.AddLastArg(CmdArgs, options::OPT_flax_vector_conversions_EQ);
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Args.AddLastArg(CmdArgs, options::OPT_fobjc_sender_dependent_dispatch);
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Args.AddLastArg(CmdArgs, options::OPT_fdiagnostics_print_source_range_info);
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@ -12224,11 +12224,30 @@ QualType Sema::CheckVectorCompareOperands(ExprResult &LHS, ExprResult &RHS,
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QualType LHSType = LHS.get()->getType();
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// If AltiVec, the comparison results in a numeric type, i.e.
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// bool for C++, int for C
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if (getLangOpts().AltiVec &&
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vType->castAs<VectorType>()->getVectorKind() == VectorType::AltiVecVector)
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return Context.getLogicalOperationType();
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// Determine the return type of a vector compare. By default clang will return
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// a scalar for all vector compares except vector bool and vector pixel.
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// With the gcc compiler we will always return a vector type and with the xl
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// compiler we will always return a scalar type. This switch allows choosing
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// which behavior is prefered.
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if (getLangOpts().AltiVec) {
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switch (getLangOpts().getAltivecSrcCompat()) {
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case LangOptions::AltivecSrcCompatKind::Mixed:
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// If AltiVec, the comparison results in a numeric type, i.e.
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// bool for C++, int for C
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if (vType->castAs<VectorType>()->getVectorKind() ==
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VectorType::AltiVecVector)
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return Context.getLogicalOperationType();
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else
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Diag(Loc, diag::warn_deprecated_altivec_src_compat);
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break;
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case LangOptions::AltivecSrcCompatKind::GCC:
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// For GCC we always return the vector type.
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break;
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case LangOptions::AltivecSrcCompatKind::XL:
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return Context.getLogicalOperationType();
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break;
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}
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}
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// For non-floating point types, check for self-comparisons of the form
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// x == x, x != x, x < x, etc. These always evaluate to a constant, and
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@ -0,0 +1,104 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
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// RUN: -faltivec-src-compat=mixed -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
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// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
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// RUN: -faltivec-src-compat=gcc -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1| FileCheck %s --check-prefix=ERROR
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// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
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// RUN: -faltivec-src-compat=xl -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
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// RUN: %clang -mcpu=pwr8 -faltivec-src-compat=xl --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
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// RUN: %clang -mcpu=pwr9 -faltivec-src-compat=xl --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
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// CHECK-LABEL: @bi8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <16 x i8>, align 16
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <16 x i8>, align 16
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// CHECK-NEXT: store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
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// CHECK-NEXT: store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
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// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
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// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
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// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequb.p(i32 2, <16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
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// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
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// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
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// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
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// CHECK-NEXT: ret i32 [[COND]]
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//
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// ERROR: error: used type '__attribute__((__vector_size__(16 * sizeof(char)))) char' (vector of 16 'char' values) where arithmetic or pointer type is required
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int bi8(vector bool char a, vector bool char b) {
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return a == b ? 3 : 7;
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}
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// CHECK-LABEL: @bi16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <8 x i16>, align 16
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// CHECK-NEXT: store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
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// CHECK-NEXT: store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
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// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
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// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
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// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequh.p(i32 2, <8 x i16> [[TMP0]], <8 x i16> [[TMP1]])
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// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
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// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
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// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
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// CHECK-NEXT: ret i32 [[COND]]
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//
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// ERROR: error: used type '__attribute__((__vector_size__(8 * sizeof(short)))) short' (vector of 8 'short' values) where arithmetic or pointer type is required
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int bi16(vector bool short a, vector bool short b) {
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return a == b ? 3 : 7;
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}
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// CHECK-LABEL: @bi32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <4 x i32>, align 16
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <4 x i32>, align 16
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// CHECK-NEXT: store <4 x i32> [[A:%.*]], <4 x i32>* [[A_ADDR]], align 16
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// CHECK-NEXT: store <4 x i32> [[B:%.*]], <4 x i32>* [[B_ADDR]], align 16
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// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[A_ADDR]], align 16
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// CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[B_ADDR]], align 16
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// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequw.p(i32 2, <4 x i32> [[TMP0]], <4 x i32> [[TMP1]])
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// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
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// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
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// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
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// CHECK-NEXT: ret i32 [[COND]]
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//
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// ERROR: error: used type '__attribute__((__vector_size__(4 * sizeof(long)))) long' (vector of 4 'long' values) where arithmetic or pointer type is required
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int bi32(vector bool int a, vector bool int b) {
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return a == b ? 3 : 7;
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}
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// CHECK-LABEL: @bi64(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <2 x i64>, align 16
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <2 x i64>, align 16
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// CHECK-NEXT: store <2 x i64> [[A:%.*]], <2 x i64>* [[A_ADDR]], align 16
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// CHECK-NEXT: store <2 x i64> [[B:%.*]], <2 x i64>* [[B_ADDR]], align 16
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// CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* [[A_ADDR]], align 16
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// CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* [[B_ADDR]], align 16
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// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequd.p(i32 2, <2 x i64> [[TMP0]], <2 x i64> [[TMP1]])
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// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
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// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
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// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
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// CHECK-NEXT: ret i32 [[COND]]
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//
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// ERROR: error: used type '__attribute__((__vector_size__(2 * sizeof(long long)))) long long' (vector of 2 'long long' values) where arithmetic or pointer type is required
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int bi64(vector bool long long a, vector bool long long b) {
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return a == b ? 3 : 7;
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}
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// CHECK-LABEL: @VecPixel(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <8 x i16>, align 16
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// CHECK-NEXT: store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
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// CHECK-NEXT: store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
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// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
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// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
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// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequh.p(i32 2, <8 x i16> [[TMP0]], <8 x i16> [[TMP1]])
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// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
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// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
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// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
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// CHECK-NEXT: ret i32 [[COND]]
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//
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// ERROR: error: used type '__attribute__((__vector_size__(8 * sizeof(short)))) short' (vector of 8 'short' values) where arithmetic or pointer type is required
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int VecPixel(vector pixel a, vector pixel b) {
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return a == b ? 3 : 7;
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}
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@ -0,0 +1,94 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
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// RUN: -faltivec-src-compat=mixed -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
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// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
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// RUN: -faltivec-src-compat=gcc -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
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// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
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// RUN: -faltivec-src-compat=xl -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
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// RUN: %clang -mcpu=pwr8 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
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// RUN: %clang -mcpu=pwr9 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
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// CHECK-LABEL: @bi8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <16 x i8>, align 16
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <16 x i8>, align 16
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// CHECK-NEXT: store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
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// CHECK-NEXT: store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
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// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
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// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
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// CHECK-NEXT: [[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
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// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
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// CHECK-NEXT: ret <16 x i8> [[SEXT]]
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//
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// ERROR: returning 'int' from a function with incompatible result type
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vector unsigned char bi8(vector bool char a, vector bool char b) {
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return a == b;
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}
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// CHECK-LABEL: @bi16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <8 x i16>, align 16
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// CHECK-NEXT: store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
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// CHECK-NEXT: store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
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// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
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// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
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// CHECK-NEXT: [[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]]
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// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16>
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// CHECK-NEXT: ret <8 x i16> [[SEXT]]
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//
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// ERROR: returning 'int' from a function with incompatible result type
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vector bool short bi16(vector bool short a, vector bool short b) {
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return a == b;
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}
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// CHECK-LABEL: @bi32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <4 x i32>, align 16
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <4 x i32>, align 16
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// CHECK-NEXT: store <4 x i32> [[A:%.*]], <4 x i32>* [[A_ADDR]], align 16
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// CHECK-NEXT: store <4 x i32> [[B:%.*]], <4 x i32>* [[B_ADDR]], align 16
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// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[A_ADDR]], align 16
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// CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[B_ADDR]], align 16
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// CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[TMP0]], [[TMP1]]
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// CHECK-NEXT: [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
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// CHECK-NEXT: ret <4 x i32> [[SEXT]]
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//
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// ERROR: returning 'int' from a function with incompatible result type
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vector bool int bi32(vector bool int a, vector bool int b) {
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return a == b;
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}
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// CHECK-LABEL: @bi64(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <2 x i64>, align 16
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <2 x i64>, align 16
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// CHECK-NEXT: store <2 x i64> [[A:%.*]], <2 x i64>* [[A_ADDR]], align 16
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// CHECK-NEXT: store <2 x i64> [[B:%.*]], <2 x i64>* [[B_ADDR]], align 16
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// CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* [[A_ADDR]], align 16
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// CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* [[B_ADDR]], align 16
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// CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i64> [[TMP0]], [[TMP1]]
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// CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i1> [[CMP]] to <2 x i64>
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// CHECK-NEXT: ret <2 x i64> [[SEXT]]
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//
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// ERROR: returning 'int' from a function with incompatible result type
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vector long long bi64(vector bool long long a, vector bool long long b) {
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||||
return a == b;
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @VecPixel(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
|
||||
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <8 x i16>, align 16
|
||||
// CHECK-NEXT: store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]]
|
||||
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16>
|
||||
// CHECK-NEXT: ret <8 x i16> [[SEXT]]
|
||||
//
|
||||
// ERROR: returning 'int' from a function with incompatible result type
|
||||
vector pixel VecPixel(vector pixel a, vector pixel b) {
|
||||
return a == b;
|
||||
}
|
||||
|
|
@ -0,0 +1,180 @@
|
|||
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
|
||||
// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
|
||||
// RUN: -faltivec-src-compat=mixed -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
|
||||
// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
|
||||
// RUN: -faltivec-src-compat=gcc -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
|
||||
// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
|
||||
// RUN: -faltivec-src-compat=xl -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
|
||||
// RUN: %clang -mcpu=pwr8 -faltivec-src-compat=xl --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
|
||||
// RUN: %clang -mcpu=pwr9 -faltivec-src-compat=xl --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
|
||||
|
||||
// CHECK-LABEL: @ui8(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <16 x i8>, align 16
|
||||
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <16 x i8>, align 16
|
||||
// CHECK-NEXT: store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequb.p(i32 2, <16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
|
||||
// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
|
||||
// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
|
||||
// CHECK-NEXT: ret i32 [[COND]]
|
||||
//
|
||||
// ERROR: error: used type '__attribute__((__vector_size__(16 * sizeof(char)))) char' (vector of 16 'char' values) where arithmetic or pointer type is required
|
||||
int ui8(vector unsigned char a, vector unsigned char b) {
|
||||
return a == b ? 3 : 7;
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @si8(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <16 x i8>, align 16
|
||||
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <16 x i8>, align 16
|
||||
// CHECK-NEXT: store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequb.p(i32 2, <16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
|
||||
// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
|
||||
// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
|
||||
// CHECK-NEXT: ret i32 [[COND]]
|
||||
//
|
||||
// ERROR: error: used type '__attribute__((__vector_size__(16 * sizeof(char)))) char' (vector of 16 'char' values) where arithmetic or pointer type is required
|
||||
int si8(vector signed char a, vector signed char b) {
|
||||
return a == b ? 3 : 7;
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @ui16(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
|
||||
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <8 x i16>, align 16
|
||||
// CHECK-NEXT: store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequh.p(i32 2, <8 x i16> [[TMP0]], <8 x i16> [[TMP1]])
|
||||
// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
|
||||
// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
|
||||
// CHECK-NEXT: ret i32 [[COND]]
|
||||
//
|
||||
// ERROR: error: used type '__attribute__((__vector_size__(8 * sizeof(short)))) short' (vector of 8 'short' values) where arithmetic or pointer type is required
|
||||
int ui16(vector unsigned short a, vector unsigned short b) {
|
||||
return a == b ? 3 : 7;
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @si16(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
|
||||
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <8 x i16>, align 16
|
||||
// CHECK-NEXT: store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequh.p(i32 2, <8 x i16> [[TMP0]], <8 x i16> [[TMP1]])
|
||||
// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
|
||||
// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
|
||||
// CHECK-NEXT: ret i32 [[COND]]
|
||||
//
|
||||
// ERROR: error: used type '__attribute__((__vector_size__(8 * sizeof(short)))) short' (vector of 8 'short' values) where arithmetic or pointer type is required
|
||||
int si16(vector signed short a, vector signed short b) {
|
||||
return a == b ? 3 : 7;
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @ui32(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <4 x i32>, align 16
|
||||
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <4 x i32>, align 16
|
||||
// CHECK-NEXT: store <4 x i32> [[A:%.*]], <4 x i32>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: store <4 x i32> [[B:%.*]], <4 x i32>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequw.p(i32 2, <4 x i32> [[TMP0]], <4 x i32> [[TMP1]])
|
||||
// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
|
||||
// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
|
||||
// CHECK-NEXT: ret i32 [[COND]]
|
||||
//
|
||||
// ERROR: error: used type '__attribute__((__vector_size__(4 * sizeof(long)))) long' (vector of 4 'long' values) where arithmetic or pointer type is required
|
||||
int ui32(vector unsigned int a, vector unsigned int b) {
|
||||
return a == b ? 3 : 7;
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @si32(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <4 x i32>, align 16
|
||||
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <4 x i32>, align 16
|
||||
// CHECK-NEXT: store <4 x i32> [[A:%.*]], <4 x i32>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: store <4 x i32> [[B:%.*]], <4 x i32>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequw.p(i32 2, <4 x i32> [[TMP0]], <4 x i32> [[TMP1]])
|
||||
// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
|
||||
// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
|
||||
// CHECK-NEXT: ret i32 [[COND]]
|
||||
//
|
||||
// ERROR: error: used type '__attribute__((__vector_size__(4 * sizeof(long)))) long' (vector of 4 'long' values) where arithmetic or pointer type is required
|
||||
int si32(vector signed int a, vector signed int b) {
|
||||
return a == b ? 3 : 7;
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @si64(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <2 x i64>, align 16
|
||||
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <2 x i64>, align 16
|
||||
// CHECK-NEXT: store <2 x i64> [[A:%.*]], <2 x i64>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: store <2 x i64> [[B:%.*]], <2 x i64>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpequd.p(i32 2, <2 x i64> [[TMP0]], <2 x i64> [[TMP1]])
|
||||
// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
|
||||
// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
|
||||
// CHECK-NEXT: ret i32 [[COND]]
|
||||
//
|
||||
// ERROR: error: used type '__attribute__((__vector_size__(2 * sizeof(long long)))) long long' (vector of 2 'long long' values) where arithmetic or pointer type is required
|
||||
int si64(vector long long a, vector long long b) {
|
||||
return a == b ? 3 : 7;
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @f32(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <4 x float>, align 16
|
||||
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <4 x float>, align 16
|
||||
// CHECK-NEXT: store <4 x float> [[A:%.*]], <4 x float>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: store <4 x float> [[B:%.*]], <4 x float>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, <4 x float>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.altivec.vcmpeqfp.p(i32 2, <4 x float> [[TMP0]], <4 x float> [[TMP1]])
|
||||
// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
|
||||
// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
|
||||
// CHECK-NEXT: ret i32 [[COND]]
|
||||
//
|
||||
// ERROR: error: used type '__attribute__((__vector_size__(4 * sizeof(long)))) long' (vector of 4 'long' values) where arithmetic or pointer type is required
|
||||
int f32(vector float a, vector float b) {
|
||||
return a == b ? 3 : 7;
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @f64(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <2 x double>, align 16
|
||||
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <2 x double>, align 16
|
||||
// CHECK-NEXT: store <2 x double> [[A:%.*]], <2 x double>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: store <2 x double> [[B:%.*]], <2 x double>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, <2 x double>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.vsx.xvcmpeqdp.p(i32 2, <2 x double> [[TMP0]], <2 x double> [[TMP1]])
|
||||
// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL]] to i64
|
||||
// CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 3, i32 7
|
||||
// CHECK-NEXT: ret i32 [[COND]]
|
||||
//
|
||||
// ERROR: error: used type '__attribute__((__vector_size__(2 * sizeof(long long)))) long long' (vector of 2 'long long' values) where arithmetic or pointer type is required
|
||||
int f64(vector double a, vector double b) {
|
||||
return a == b ? 3 : 7;
|
||||
}
|
||||
|
|
@ -0,0 +1,162 @@
|
|||
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
|
||||
// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
|
||||
// RUN: -faltivec-src-compat=mixed -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
|
||||
// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
|
||||
// RUN: -faltivec-src-compat=gcc -triple powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
|
||||
// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
|
||||
// RUN: -faltivec-src-compat=xl -triple powerpc-unknown-unknown -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
|
||||
// RUN: %clang -mcpu=pwr8 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
|
||||
// RUN: %clang -mcpu=pwr9 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
|
||||
|
||||
// CHECK-LABEL: @ui8(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <16 x i8>, align 16
|
||||
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <16 x i8>, align 16
|
||||
// CHECK-NEXT: store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
|
||||
// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
|
||||
// CHECK-NEXT: ret <16 x i8> [[SEXT]]
|
||||
//
|
||||
// ERROR: returning 'int' from a function with incompatible result type
|
||||
vector unsigned char ui8(vector unsigned char a, vector unsigned char b) {
|
||||
return a == b;
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @si8(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <16 x i8>, align 16
|
||||
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <16 x i8>, align 16
|
||||
// CHECK-NEXT: store <16 x i8> [[A:%.*]], <16 x i8>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: store <16 x i8> [[B:%.*]], <16 x i8>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
|
||||
// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
|
||||
// CHECK-NEXT: ret <16 x i8> [[SEXT]]
|
||||
//
|
||||
// ERROR: returning 'int' from a function with incompatible result type
|
||||
vector signed char si8(vector signed char a, vector signed char b) {
|
||||
return a == b;
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @ui16(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
|
||||
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <8 x i16>, align 16
|
||||
// CHECK-NEXT: store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]]
|
||||
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16>
|
||||
// CHECK-NEXT: ret <8 x i16> [[SEXT]]
|
||||
//
|
||||
// ERROR: returning 'int' from a function with incompatible result type
|
||||
vector unsigned short ui16(vector unsigned short a, vector unsigned short b) {
|
||||
return a == b;
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @si16(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
|
||||
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <8 x i16>, align 16
|
||||
// CHECK-NEXT: store <8 x i16> [[A:%.*]], <8 x i16>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: store <8 x i16> [[B:%.*]], <8 x i16>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]]
|
||||
// CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16>
|
||||
// CHECK-NEXT: ret <8 x i16> [[SEXT]]
|
||||
//
|
||||
// ERROR: returning 'int' from a function with incompatible result type
|
||||
vector signed short si16(vector signed short a, vector signed short b) {
|
||||
return a == b;
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @ui32(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <4 x i32>, align 16
|
||||
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <4 x i32>, align 16
|
||||
// CHECK-NEXT: store <4 x i32> [[A:%.*]], <4 x i32>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: store <4 x i32> [[B:%.*]], <4 x i32>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[TMP0]], [[TMP1]]
|
||||
// CHECK-NEXT: [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
|
||||
// CHECK-NEXT: ret <4 x i32> [[SEXT]]
|
||||
//
|
||||
// ERROR: returning 'int' from a function with incompatible result type
|
||||
vector unsigned int ui32(vector unsigned int a, vector unsigned int b) {
|
||||
return a == b;
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @si32(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <4 x i32>, align 16
|
||||
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <4 x i32>, align 16
|
||||
// CHECK-NEXT: store <4 x i32> [[A:%.*]], <4 x i32>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: store <4 x i32> [[B:%.*]], <4 x i32>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[TMP0]], [[TMP1]]
|
||||
// CHECK-NEXT: [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
|
||||
// CHECK-NEXT: ret <4 x i32> [[SEXT]]
|
||||
//
|
||||
// ERROR: returning 'int' from a function with incompatible result type
|
||||
vector signed int si32(vector signed int a, vector signed int b) {
|
||||
return a == b;
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @si64(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <2 x i64>, align 16
|
||||
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <2 x i64>, align 16
|
||||
// CHECK-NEXT: store <2 x i64> [[A:%.*]], <2 x i64>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: store <2 x i64> [[B:%.*]], <2 x i64>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i64> [[TMP0]], [[TMP1]]
|
||||
// CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i1> [[CMP]] to <2 x i64>
|
||||
// CHECK-NEXT: ret <2 x i64> [[SEXT]]
|
||||
//
|
||||
// ERROR: returning 'int' from a function with incompatible result type
|
||||
vector long long si64(vector long long a, vector long long b) {
|
||||
return a == b;
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @f32(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <4 x float>, align 16
|
||||
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <4 x float>, align 16
|
||||
// CHECK-NEXT: store <4 x float> [[A:%.*]], <4 x float>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: store <4 x float> [[B:%.*]], <4 x float>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, <4 x float>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[CMP:%.*]] = fcmp oeq <4 x float> [[TMP0]], [[TMP1]]
|
||||
// CHECK-NEXT: [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
|
||||
// CHECK-NEXT: ret <4 x i32> [[SEXT]]
|
||||
//
|
||||
// ERROR: returning 'int' from a function with incompatible result type
|
||||
vector int f32(vector float a, vector float b) {
|
||||
return a == b;
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @f64(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <2 x double>, align 16
|
||||
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca <2 x double>, align 16
|
||||
// CHECK-NEXT: store <2 x double> [[A:%.*]], <2 x double>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: store <2 x double> [[B:%.*]], <2 x double>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* [[A_ADDR]], align 16
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, <2 x double>* [[B_ADDR]], align 16
|
||||
// CHECK-NEXT: [[CMP:%.*]] = fcmp oeq <2 x double> [[TMP0]], [[TMP1]]
|
||||
// CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i1> [[CMP]] to <2 x i64>
|
||||
// CHECK-NEXT: ret <2 x i64> [[SEXT]]
|
||||
//
|
||||
// ERROR: returning 'int' from a function with incompatible result type
|
||||
vector long long f64(vector double a, vector double b) {
|
||||
return a == b;
|
||||
}
|
||||
Loading…
Reference in New Issue