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[X86][SSE] Add extra computeNumSignBits test case for D31311. 

llvm-svn: 298774
This commit is contained in:
Simon Pilgrim 2017-03-25 15:43:36 +00:00
parent 354097b05d
commit c3e5c3c5bc
1 changed files with 47 additions and 0 deletions
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47
llvm/test/CodeGen/X86/known-signbits-vector.ll
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@ -96,3 +96,50 @@ define float @signbits_ashr_extract_sitofp(<2 x i64> %a0) nounwind {
%3 = sitofp i64 %2 to float
ret float %3
}
define float @signbits_ashr_insert_ashr_extract_sitofp(i64 %a0, i64 %a1) nounwind {
; X32-LABEL: signbits_ashr_insert_ashr_extract_sitofp:
; X32: # BB#0:
; X32-NEXT: pushl %ebp
; X32-NEXT: movl %esp, %ebp
; X32-NEXT: andl $-8, %esp
; X32-NEXT: subl $16, %esp
; X32-NEXT: movl 8(%ebp), %eax
; X32-NEXT: movl 12(%ebp), %ecx
; X32-NEXT: shrdl $30, %ecx, %eax
; X32-NEXT: sarl $30, %ecx
; X32-NEXT: vmovd %eax, %xmm0
; X32-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
; X32-NEXT: vpinsrd $2, 16(%ebp), %xmm0, %xmm0
; X32-NEXT: vpinsrd $3, 20(%ebp), %xmm0, %xmm0
; X32-NEXT: vpsrad $3, %xmm0, %xmm1
; X32-NEXT: vpsrlq $3, %xmm0, %xmm0
; X32-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; X32-NEXT: vmovq %xmm0, {{[0-9]+}}(%esp)
; X32-NEXT: fildll {{[0-9]+}}(%esp)
; X32-NEXT: fstps {{[0-9]+}}(%esp)
; X32-NEXT: flds {{[0-9]+}}(%esp)
; X32-NEXT: movl %ebp, %esp
; X32-NEXT: popl %ebp
; X32-NEXT: retl
;
; X64-LABEL: signbits_ashr_insert_ashr_extract_sitofp:
; X64: # BB#0:
; X64-NEXT: sarq $30, %rdi
; X64-NEXT: vmovq %rsi, %xmm0
; X64-NEXT: vmovq %rdi, %xmm1
; X64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; X64-NEXT: vpsrad $3, %xmm0, %xmm1
; X64-NEXT: vpsrlq $3, %xmm0, %xmm0
; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; X64-NEXT: vmovq %xmm0, %rax
; X64-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0
; X64-NEXT: retq
%1 = ashr i64 %a0, 30
%2 = insertelement <2 x i64> undef, i64 %1, i32 0
%3 = insertelement <2 x i64> %2, i64 %a1, i32 1
%4 = ashr <2 x i64> %3, <i64 3, i64 3>
%5 = extractelement <2 x i64> %4, i32 0
%6 = sitofp i64 %5 to float
ret float %6
}