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Fix encoding of Thumb2 shifted register operands with RRX shifts. 

llvm-svn: 139606
This commit is contained in:
Owen Anderson 2011-09-13 17:34:32 +00:00
parent 79a91418bd
commit c3c60a0882
2 changed files with 9 additions and 0 deletions
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1
llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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@ -1277,6 +1277,7 @@ getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
case ARM_AM::lsl: SBits = 0x0; break;
case ARM_AM::lsr: SBits = 0x2; break;
case ARM_AM::asr: SBits = 0x4; break;
case ARM_AM::rrx: // FALLTHROUGH
case ARM_AM::ror: SBits = 0x6; break;
}

8
llvm/test/MC/ARM/basic-thumb2-instructions.s
View File

@ -1029,3 +1029,11 @@ _func:
@ CHECK: nopne @ encoding: [0x00,0xbf]
@ CHECK: subne r5, r6, r7 @ encoding: [0xf5,0x1b]
@ CHECK: addeq r1, r2, #4 @ encoding: [0x11,0x1d]
@------------------------------------------------------------------------------
@ SUB (register)
@------------------------------------------------------------------------------
sub.w r5, r2, r12, rrx
@ CHECK: sub.w r5, r2, r12, rrx @ encoding: [0xa2,0xeb,0x3c,0x05]