forked from OSchip/llvm-project
[RISCV] Add support for RVC HINT instructions
The hint instructions are enabled by default (if the standard C extension is enabled). To disable them pass -mattr=-rvc-hints. Differential Revision: https://reviews.llvm.org/D62592 llvm-svn: 369528
This commit is contained in:
Luis Marques
parent
a451156bb6
commit
c3bf3d14ea
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@ -864,6 +864,10 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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return generateImmOutOfRangeError(Operands, ErrorInfo,
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std::numeric_limits<int32_t>::min(),
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std::numeric_limits<uint32_t>::max());
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case Match_InvalidImmZero: {
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SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
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return Error(ErrorLoc, "immediate must be zero");
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}
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case Match_InvalidUImmLog2XLen:
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if (isRV64())
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return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 6) - 1);
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@ -280,8 +280,77 @@ static DecodeStatus decodeFRMArg(MCInst &Inst, uint64_t Imm,
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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#include "RISCVGenDisassemblerTables.inc"
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static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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uint64_t SImm6 =
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fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
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assert(decodeSImmOperand<6>(Inst, SImm6, Address, Decoder) ==
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MCDisassembler::Success && "Invalid immediate");
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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DecodeGPRRegisterClass(Inst, 0, Address, Decoder);
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uint64_t SImm6 =
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fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
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assert(decodeSImmOperand<6>(Inst, SImm6, Address, Decoder) ==
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MCDisassembler::Success && "Invalid immediate");
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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DecodeGPRRegisterClass(Inst, 0, Address, Decoder);
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Inst.addOperand(Inst.getOperand(0));
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uint64_t UImm6 =
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fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
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assert(decodeUImmOperand<6>(Inst, UImm6, Address, Decoder) ==
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MCDisassembler::Success && "Invalid immediate");
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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unsigned Rd = fieldFromInstruction(Insn, 7, 5);
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unsigned Rs2 = fieldFromInstruction(Insn, 2, 5);
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DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
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DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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unsigned Rd = fieldFromInstruction(Insn, 7, 5);
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unsigned Rs2 = fieldFromInstruction(Insn, 2, 5);
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DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
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Inst.addOperand(Inst.getOperand(0));
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DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
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return MCDisassembler::Success;
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}
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DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address,
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@ -43,6 +43,11 @@ def FeatureStdExtC
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def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
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AssemblerPredicate<"FeatureStdExtC">;
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def FeatureRVCHints
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: SubtargetFeature<"rvc-hints", "EnableRVCHintInstrs", "true",
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"Enable RVC Hint Instructions.">;
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def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
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AssemblerPredicate<"FeatureRVCHints">;
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def Feature64Bit
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: SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
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@ -83,9 +88,10 @@ include "RISCVRegisterBanks.td"
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// RISC-V processors supported.
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//===----------------------------------------------------------------------===//
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def : ProcessorModel<"generic-rv32", NoSchedModel, []>;
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def : ProcessorModel<"generic-rv32", NoSchedModel, [FeatureRVCHints]>;
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def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
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def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit,
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FeatureRVCHints]>;
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//===----------------------------------------------------------------------===//
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// Define the RISC-V target.
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@ -69,6 +69,12 @@ class ImmAsmOperand<string prefix, int width, string suffix> : AsmOperandClass {
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let DiagnosticType = !strconcat("Invalid", Name);
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}
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def ImmZeroAsmOperand : AsmOperandClass {
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let Name = "ImmZero";
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let RenderMethod = "addImmOperands";
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let DiagnosticType = !strconcat("Invalid", Name);
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}
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class SImmAsmOperand<int width, string suffix = "">
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: ImmAsmOperand<"S", width, suffix> {
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}
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@ -61,6 +61,11 @@ def simm6nonzero : Operand<XLenVT>,
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}];
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}
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def immzero : Operand<XLenVT>,
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ImmLeaf<XLenVT, [{return (Imm == 0);}]> {
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let ParserMatchClass = ImmZeroAsmOperand;
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}
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def CLUIImmAsmOperand : AsmOperandClass {
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let Name = "CLUIImm";
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let RenderMethod = "addImmOperands";
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@ -344,7 +349,10 @@ def C_SD : CStore_rri<0b111, "c.sd", GPRC, uimm8_lsb000> {
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}
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let rd = 0, imm = 0, hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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def C_NOP : RVInst16CI<0b000, 0b01, (outs), (ins), "c.nop", "">;
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def C_NOP : RVInst16CI<0b000, 0b01, (outs), (ins), "c.nop", "">
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{
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let Inst{6-2} = 0;
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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def C_ADDI : RVInst16CI<0b000, 0b01, (outs GPRNoX0:$rd_wb),
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@ -354,6 +362,15 @@ def C_ADDI : RVInst16CI<0b000, 0b01, (outs GPRNoX0:$rd_wb),
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let Inst{6-2} = imm{4-0};
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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def C_ADDI_NOP : RVInst16CI<0b000, 0b01, (outs GPRX0:$rd_wb),
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(ins GPRX0:$rd, immzero:$imm),
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"c.addi", "$rd, $imm"> {
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let Constraints = "$rd = $rd_wb";
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let Inst{6-2} = 0;
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let isAsmParserOnly = 1;
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCall = 1,
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DecoderNamespace = "RISCV32Only_", Defs = [X1],
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Predicates = [HasStdExtC, IsRV32] in
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@ -522,6 +539,105 @@ def C_UNIMP : RVInst16<(outs), (ins), "c.unimp", "", [], InstFormatOther> {
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} // Predicates = [HasStdExtC]
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//===----------------------------------------------------------------------===//
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// HINT Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtC, HasRVCHints], hasSideEffects = 0, mayLoad = 0,
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mayStore = 0 in
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{
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let rd = 0 in
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def C_NOP_HINT : RVInst16CI<0b000, 0b01, (outs), (ins simm6nonzero:$imm),
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"c.nop", "$imm"> {
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let Inst{6-2} = imm{4-0};
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let DecoderMethod = "decodeRVCInstrSImm";
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}
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// Just a different syntax for the c.nop hint: c.addi x0, simm6 vs c.nop simm6.
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def C_ADDI_HINT_X0 : RVInst16CI<0b000, 0b01, (outs GPRX0:$rd_wb),
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(ins GPRX0:$rd, simm6nonzero:$imm),
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"c.addi", "$rd, $imm"> {
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let Constraints = "$rd = $rd_wb";
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let Inst{6-2} = imm{4-0};
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let isAsmParserOnly = 1;
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}
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def C_ADDI_HINT_IMM_ZERO : RVInst16CI<0b000, 0b01, (outs GPRNoX0:$rd_wb),
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(ins GPRNoX0:$rd, immzero:$imm),
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"c.addi", "$rd, $imm"> {
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let Constraints = "$rd = $rd_wb";
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let Inst{6-2} = 0;
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let isAsmParserOnly = 1;
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}
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def C_LI_HINT : RVInst16CI<0b010, 0b01, (outs GPRX0:$rd), (ins simm6:$imm),
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"c.li", "$rd, $imm"> {
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let Inst{6-2} = imm{4-0};
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let Inst{11-7} = 0;
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let DecoderMethod = "decodeRVCInstrRdSImm";
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}
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def C_LUI_HINT : RVInst16CI<0b011, 0b01, (outs GPRX0:$rd),
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(ins c_lui_imm:$imm),
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"c.lui", "$rd, $imm"> {
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let Inst{6-2} = imm{4-0};
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let Inst{11-7} = 0;
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let DecoderMethod = "decodeRVCInstrRdSImm";
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}
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def C_MV_HINT : RVInst16CR<0b1000, 0b10, (outs GPRX0:$rs1), (ins GPRNoX0:$rs2),
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"c.mv", "$rs1, $rs2">
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{
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let Inst{11-7} = 0;
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let DecoderMethod = "decodeRVCInstrRdRs2";
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}
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def C_ADD_HINT : RVInst16CR<0b1001, 0b10, (outs GPRX0:$rs1_wb),
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(ins GPRX0:$rs1, GPRNoX0:$rs2),
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"c.add", "$rs1, $rs2"> {
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let Constraints = "$rs1 = $rs1_wb";
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let Inst{11-7} = 0;
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let DecoderMethod = "decodeRVCInstrRdRs1Rs2";
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}
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def C_SLLI_HINT : RVInst16CI<0b000, 0b10, (outs GPRX0:$rd_wb),
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(ins GPRX0:$rd, uimmlog2xlennonzero:$imm),
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"c.slli" ,"$rd, $imm"> {
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let Constraints = "$rd = $rd_wb";
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let Inst{6-2} = imm{4-0};
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let Inst{11-7} = 0;
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let DecoderMethod = "decodeRVCInstrRdRs1UImm";
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}
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def C_SLLI64_HINT : RVInst16CI<0b000, 0b10, (outs GPR:$rd_wb), (ins GPR:$rd),
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"c.slli64" ,"$rd"> {
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let Constraints = "$rd = $rd_wb";
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let Inst{6-2} = 0;
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let Inst{12} = 0;
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}
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def C_SRLI64_HINT : RVInst16CI<0b100, 0b01, (outs GPRC:$rd_wb),
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(ins GPRC:$rd),
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"c.srli64", "$rd"> {
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let Constraints = "$rd = $rd_wb";
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let Inst{6-2} = 0;
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let Inst{11-10} = 0;
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let Inst{12} = 0;
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}
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def C_SRAI64_HINT : RVInst16CI<0b100, 0b01, (outs GPRC:$rd_wb),
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(ins GPRC:$rd),
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"c.srai64", "$rd"> {
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let Constraints = "$rd = $rd_wb";
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let Inst{6-2} = 0;
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let Inst{11-10} = 1;
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let Inst{12} = 0;
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}
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} // Predicates = [HasStdExtC, HasRVCHints], hasSideEffects = 0, mayLoad = 0,
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// mayStore = 0
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//===----------------------------------------------------------------------===//
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// Assembler Pseudo Instructions
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//===----------------------------------------------------------------------===//
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@ -101,6 +101,12 @@ def GPR : RegisterClass<"RISCV", [XLenVT], 32, (add
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[RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
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}
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def GPRX0 : RegisterClass<"RISCV", [XLenVT], 32, (add X0)> {
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let RegInfos = RegInfoByHwMode<
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[RV32, RV64, DefaultMode],
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[RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
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}
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// The order of registers represents the preferred allocation sequence.
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// Registers are listed in the order caller-save, callee-save, specials.
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def GPRNoX0 : RegisterClass<"RISCV", [XLenVT], 32, (add
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@ -42,6 +42,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
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bool HasRV64 = false;
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bool IsRV32E = false;
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bool EnableLinkerRelax = false;
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bool EnableRVCHintInstrs = false;
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unsigned XLen = 32;
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MVT XLenVT = MVT::i32;
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RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
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@ -87,6 +88,7 @@ public:
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bool is64Bit() const { return HasRV64; }
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bool isRV32E() const { return IsRV32E; }
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bool enableLinkerRelax() const { return EnableLinkerRelax; }
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bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
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MVT getXLenVT() const { return XLenVT; }
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unsigned getXLen() const { return XLen; }
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RISCVABI::ABI getTargetABI() const { return TargetABI; }
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@ -1,4 +1,5 @@
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# RUN: not llvm-mc -triple=riscv32 -mattr=+c < %s 2>&1 | FileCheck %s
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# RUN: not llvm-mc -triple=riscv32 -mattr=+c -mattr=-rvc-hints < %s 2>&1 \
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# RUN: | FileCheck %s
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## GPRC
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.LBB:
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@ -20,16 +21,16 @@ c.lwsp x0, 4(sp) # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
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c.lwsp zero, 4(sp) # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
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c.jr x0 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
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c.jalr zero # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
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c.addi x0, x0, 1 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
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c.li zero, 2 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
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c.slli zero, zero, 4 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
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c.mv zero, s0 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
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c.addi x0, x0, 1 # CHECK: :[[@LINE]]:13: error: immediate must be zero
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c.li zero, 2 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
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c.slli zero, zero, 4 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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c.mv zero, s0 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
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c.mv ra, x0 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
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c.add ra, ra, x0 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
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c.add zero, zero, sp # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
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c.add zero, zero, sp # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
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## GPRNoX0X2
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c.lui x0, 4 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
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c.lui x0, 4 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
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c.lui x2, 4 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
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## SP
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@ -54,7 +55,7 @@ c.andi a0, %lo(foo) # CHECK: :[[@LINE]]:12: error: immediate must be an integer
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c.andi a0, %hi(foo) # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [-32, 31]
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## simm6nonzero
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c.addi t0, 0 # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31]
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c.addi t0, 0 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
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c.addi t0, -33 # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31]
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c.addi t0, 32 # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31]
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c.addi t0, foo # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31]
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@ -0,0 +1,9 @@
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# RUN: llvm-mc %s -triple riscv64 -mattr=+c -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
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# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c < %s \
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# RUN: | llvm-objdump -riscv-no-aliases -d -r - \
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# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
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# CHECK-ASM-AND-OBJ: c.slli zero, 63
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# CHECK-ASM: encoding: [0x7e,0x10]
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c.slli x0, 63
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@ -0,0 +1,25 @@
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# RUN: not llvm-mc -triple=riscv32 -mattr=+c < %s 2>&1 \
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-RV32 %s
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# RUN: not llvm-mc -triple=riscv64 -mattr=+c < %s 2>&1 \
|
||||
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-RV64 %s
|
||||
|
||||
c.nop 0 # CHECK: :[[@LINE]]:7: error: immediate must be non-zero in the range [-32, 31]
|
||||
|
||||
c.addi x0, 33 # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31]
|
||||
|
||||
c.li x0, 42 # CHECK: :[[@LINE]]:10: error: immediate must be an integer in the range [-32, 31]
|
||||
|
||||
c.lui x0, 0 # CHECK: :[[@LINE]]:11: error: immediate must be in [0xfffe0, 0xfffff] or [1, 31]
|
||||
|
||||
c.mv x0, x0 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
|
||||
|
||||
c.add x0, x0 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
|
||||
|
||||
c.slli x0, 0 # CHECK-RV32: :[[@LINE]]:12: error: immediate must be an integer in the range [1, 31]
|
||||
c.slli x0, 32 # CHECK-RV32: :[[@LINE]]:12: error: immediate must be an integer in the range [1, 31]
|
||||
|
||||
c.slli x0, 0 # CHECK-RV64: :[[@LINE]]:12: error: immediate must be an integer in the range [1, 63]
|
||||
|
||||
c.srli64 x30 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
|
||||
|
||||
c.srai64 x31 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
# RUN: llvm-mc %s -triple=riscv32 -mattr=+c -riscv-no-aliases -show-encoding \
|
||||
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
|
||||
# RUN: llvm-mc %s -triple riscv64 -mattr=+c -riscv-no-aliases -show-encoding \
|
||||
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
|
||||
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+c < %s \
|
||||
# RUN: | llvm-objdump -riscv-no-aliases -d -r - \
|
||||
# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
|
||||
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c < %s \
|
||||
# RUN: | llvm-objdump -riscv-no-aliases -d -r - \
|
||||
# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
|
||||
|
||||
# CHECK-ASM-AND-OBJ: c.nop 8
|
||||
# CHECK-ASM: encoding: [0x21,0x00]
|
||||
c.nop 8
|
||||
|
||||
# CHECK-ASM: c.addi zero, 7
|
||||
# CHECK-ASM: encoding: [0x1d,0x00]
|
||||
# CHECK-OBJ: c.nop 7
|
||||
c.addi x0, 7
|
||||
|
||||
# CHECK-ASM-AND-OBJ: c.addi a0, 0
|
||||
# CHECK-ASM: encoding: [0x01,0x05]
|
||||
c.addi a0, 0
|
||||
|
||||
# CHECK-ASM-AND-OBJ: c.li zero, 0
|
||||
# CHECK-ASM: encoding: [0x01,0x40]
|
||||
c.li x0, 0
|
||||
|
||||
# CHECK-ASM-AND-OBJ: c.li zero, 1
|
||||
# CHECK-ASM: encoding: [0x05,0x40]
|
||||
c.li x0, 1
|
||||
|
||||
# CHECK-ASM-AND-OBJ: c.lui zero, 1
|
||||
# CHECK-ASM: encoding: [0x05,0x60]
|
||||
c.lui x0, 1
|
||||
|
||||
# CHECK-ASM-AND-OBJ: c.mv zero, a0
|
||||
# CHECK-ASM: encoding: [0x2a,0x80]
|
||||
c.mv x0, a0
|
||||
|
||||
# CHECK-ASM-AND-OBJ: c.add zero, a0
|
||||
# CHECK-ASM: encoding: [0x2a,0x90]
|
||||
c.add x0, a0
|
||||
|
||||
# CHECK-ASM-AND-OBJ: c.slli zero, 1
|
||||
# CHECK-ASM: encoding: [0x06,0x00]
|
||||
c.slli x0, 1
|
||||
|
||||
# CHECK-ASM-AND-OBJ: c.slli64 zero
|
||||
# CHECK-ASM: encoding: [0x02,0x00]
|
||||
c.slli64 x0
|
||||
|
||||
# CHECK-ASM-AND-OBJ: c.slli64 a0
|
||||
# CHECK-ASM: encoding: [0x02,0x05]
|
||||
c.slli64 a0
|
||||
|
||||
# CHECK-ASM-AND-OBJ: c.srli64 a1
|
||||
# CHECK-ASM: encoding: [0x81,0x81]
|
||||
c.srli64 a1
|
||||
|
||||
# CHECK-ASM-AND-OBJ: c.srai64 a0
|
||||
# CHECK-ASM: encoding: [0x01,0x85]
|
||||
c.srai64 a0
|
||||
Loading…
Reference in New Issue