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Fix a missing MemorySSA update in breakLoopBackedge 

This is a case I'd missed in 6a8237. The odd bit here is that missing the edge removal update seems to produce MemorySSA which verifies, but is still corrupt in a way which bothers following passes. I wasn't able to reduce a single pass test case, which is why the reported test case is taken as is.

Differential Revision: https://reviews.llvm.org/D109068
This commit is contained in:
Philip Reames 2021-09-01 16:58:04 -07:00
parent 91f4655d92
commit c3b3aa277a
2 changed files with 32 additions and 2 deletions
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7
llvm/lib/Transforms/Utils/LoopUtils.cpp
View File

@ -729,8 +729,9 @@ void llvm::breakLoopBackedge(Loop *L, DominatorTree &DT, ScalarEvolution &SE,
// and outer loop so the other target doesn't need to an exit
if (L->isLoopExiting(Latch)) {
// TODO: Generalize ConstantFoldTerminator so that it can be used
// here without invalidating LCSSA. (Tricky case: header is an exit
// block of a preceeding sibling loop w/o dedicated exits.)
// here without invalidating LCSSA or MemorySSA. (Tricky case for
// LCSSA: header is an exit block of a preceeding sibling loop w/o
// dedicated exits.)
const unsigned ExitIdx = L->contains(BI->getSuccessor(0)) ? 1 : 0;
BasicBlock *ExitBB = BI->getSuccessor(ExitIdx);
@ -746,6 +747,8 @@ void llvm::breakLoopBackedge(Loop *L, DominatorTree &DT, ScalarEvolution &SE,
BI->eraseFromParent();
DTU.applyUpdates({{DominatorTree::Delete, Latch, Header}});
if (MSSA)
MSSAU->applyUpdates({{DominatorTree::Delete, Latch, Header}}, DT);
return;
}
}

27
llvm/test/Transforms/LoopDeletion/bbi-59728.ll Normal file
View File

@ -0,0 +1,27 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt %s -verify-memoryssa -passes='loop-mssa(loop-deletion,loop-simplifycfg)' -S | FileCheck %s
; This is a case where we failed to update memory SSA correctly in
; loop-deletion which escapes local verification, but causes a crash
; in loop-simplifycfg.
define void @func_45() {
; CHECK-LABEL: @func_45(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[FOR_BODY45:%.*]]
; CHECK: for.body45:
; CHECK-NEXT: store i32 433429641, i32* undef, align 1
; CHECK-NEXT: br label [[FOR_BODY45]]
;
entry:
br label %for.body45
for.body45: ; preds = %for.end72, %entry
br label %for.body48
for.body48: ; preds = %for.body48, %for.body45
store i32 433429641, i32* undef, align 1
br i1 undef, label %for.body48, label %for.end72
for.end72: ; preds = %for.body48
br label %for.body45
}