maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

Allow MCCodeEmitter access to the target MCRegisterInfo. 

Add the MCRegisterInfo to the factories and constructors.

Patch by Tom Stellard <Tom.Stellard@amd.com>.

llvm-svn: 156828
This commit is contained in:
Jim Grosbach 2012-05-15 17:35:52 +00:00
parent 9b88cc0a40
commit c3b0427921
13 changed files with 30 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
llvm/include/llvm/Support/TargetRegistry.h
View File

@ -108,6 +108,7 @@ namespace llvm {
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI);
typedef MCCodeEmitter *(*MCCodeEmitterCtorTy)(const MCInstrInfo &II,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx);
typedef MCStreamer *(*MCObjectStreamerCtorTy)(const Target &T,
@ -405,11 +406,12 @@ namespace llvm {
/// createMCCodeEmitter - Create a target specific code emitter.
MCCodeEmitter *createMCCodeEmitter(const MCInstrInfo &II,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx) const {
if (!MCCodeEmitterCtorFn)
return 0;
return MCCodeEmitterCtorFn(II, STI, Ctx);
return MCCodeEmitterCtorFn(II, MRI, STI, Ctx);
}
/// createMCObjectStreamer - Create a target specific MCStreamer.
@ -1144,6 +1146,7 @@ namespace llvm {
private:
static MCCodeEmitter *Allocator(const MCInstrInfo &II,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx) {
return new MCCodeEmitterImpl();

13
llvm/lib/CodeGen/LLVMTargetMachine.cpp
View File

@ -165,6 +165,7 @@ bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
Context->setAllowTemporaryLabels(false);
const MCAsmInfo &MAI = *getMCAsmInfo();
const MCRegisterInfo &MRI = *getTarget().createMCRegInfo(getTargetTriple());
const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
OwningPtr<MCStreamer> AsmStreamer;
@ -180,7 +181,8 @@ bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
MCAsmBackend *MAB = 0;
if (ShowMCEncoding) {
const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), STI, *Context);
MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), MRI, STI,
*Context);
MAB = getTarget().createMCAsmBackend(getTargetTriple());
}
@ -198,8 +200,8 @@ bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
case CGFT_ObjectFile: {
// Create the code emitter for the target if it exists. If not, .o file
// emission fails.
MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), STI,
*Context);
MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), MRI,
STI, *Context);
MCAsmBackend *MAB = getTarget().createMCAsmBackend(getTargetTriple());
if (MCE == 0 || MAB == 0)
return true;
@ -271,9 +273,10 @@ bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM,
// Create the code emitter for the target if it exists. If not, .o file
// emission fails.
const MCRegisterInfo &MRI = *getTarget().createMCRegInfo(getTargetTriple());
const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(),STI,
*Ctx);
MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), MRI,
STI, *Ctx);
MCAsmBackend *MAB = getTarget().createMCAsmBackend(getTargetTriple());
if (MCE == 0 || MAB == 0)
return true;

1
llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
View File

@ -336,6 +336,7 @@ public:
} // end anonymous namespace
MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx) {
return new ARMMCCodeEmitter(MCII, STI, Ctx);

2
llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
View File

@ -23,6 +23,7 @@ class MCCodeEmitter;
class MCContext;
class MCInstrInfo;
class MCObjectWriter;
class MCRegisterInfo;
class MCSubtargetInfo;
class StringRef;
class Target;
@ -41,6 +42,7 @@ namespace ARM_MC {
}
MCCodeEmitter *createARMMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx);

1
llvm/lib/Target/MBlaze/MCTargetDesc/MBlazeMCCodeEmitter.cpp
View File

@ -98,6 +98,7 @@ public:
MCCodeEmitter *llvm::createMBlazeMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx) {
return new MBlazeMCCodeEmitter(MCII, STI, Ctx);

2
llvm/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h
View File

@ -22,6 +22,7 @@ class MCContext;
class MCCodeEmitter;
class MCInstrInfo;
class MCObjectWriter;
class MCRegisterInfo;
class MCSubtargetInfo;
class Target;
class StringRef;
@ -30,6 +31,7 @@ class raw_ostream;
extern Target TheMBlazeTarget;
MCCodeEmitter *createMBlazeMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx);

2
llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
View File

@ -91,6 +91,7 @@ public:
} // namespace
MCCodeEmitter *llvm::createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx)
{
@ -98,6 +99,7 @@ MCCodeEmitter *llvm::createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
}
MCCodeEmitter *llvm::createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx)
{

3
llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
View File

@ -22,6 +22,7 @@ class MCCodeEmitter;
class MCContext;
class MCInstrInfo;
class MCObjectWriter;
class MCRegisterInfo;
class MCSubtargetInfo;
class StringRef;
class Target;
@ -33,9 +34,11 @@ extern Target TheMips64Target;
extern Target TheMips64elTarget;
MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx);
MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx);

1
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
View File

@ -77,6 +77,7 @@ public:
} // end anonymous namespace
MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx) {
return new PPCMCCodeEmitter(MCII, STI, Ctx);

2
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
View File

@ -22,6 +22,7 @@ class MCCodeEmitter;
class MCContext;
class MCInstrInfo;
class MCObjectWriter;
class MCRegisterInfo;
class MCSubtargetInfo;
class Target;
class StringRef;
@ -31,6 +32,7 @@ extern Target ThePPC32Target;
extern Target ThePPC64Target;
MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx);

1
llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
View File

@ -139,6 +139,7 @@ public:
MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx) {
return new X86MCCodeEmitter(MCII, STI, Ctx);

1
llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
View File

@ -76,6 +76,7 @@ namespace X86_MC {
}
MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx);

4
llvm/tools/llvm-mc/llvm-mc.cpp
View File

@ -408,7 +408,7 @@ int main(int argc, char **argv) {
MCCodeEmitter *CE = 0;
MCAsmBackend *MAB = 0;
if (ShowEncoding) {
CE = TheTarget->createMCCodeEmitter(*MCII, *STI, Ctx);
CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx);
MAB = TheTarget->createMCAsmBackend(TripleName);
}
Str.reset(TheTarget->createAsmStreamer(Ctx, FOS, /*asmverbose*/true,
@ -421,7 +421,7 @@ int main(int argc, char **argv) {
Str.reset(createNullStreamer(Ctx));
} else {
assert(FileType == OFT_ObjectFile && "Invalid file type!");
MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *STI, Ctx);
MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx);
MCAsmBackend *MAB = TheTarget->createMCAsmBackend(TripleName);
Str.reset(TheTarget->createMCObjectStreamer(TripleName, Ctx, *MAB,
FOS, CE, RelaxAll,