forked from OSchip/llvm-project
[lanai] Add more tests for assembly of conditional ALU ops
llvm-svn: 275081
This commit is contained in:
Jacques Pienaar
parent
02989a4b5d
commit
c3a162c451
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@ -0,0 +1,77 @@
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! RUN: llvm-mc -arch=lanai -show-encoding -show-inst < %s | FileCheck %s
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.text
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.align 4
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.global jump1
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bt %r5
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! CHECK: encoding: [0xc1,0x00,0x2d,0x00]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} JR{{$}}
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! CHECK-NEXT: <MCOperand Reg:12>>
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! BR classes
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bt 0x1234
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! CHECK: encoding: [0xe0,0x00,0x12,0x34]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} BT{{$}}
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! CHECK-NEXT: <MCOperand Imm:4660>
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jump1:
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blt 2000
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! CHECK: encoding: [0xec,0x00,0x07,0xd1]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} BRCC{{$}}
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! CHECK-NEXT: <MCOperand Imm:2000>
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! CHECK-NEXT: <MCOperand Imm:13>
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jump2:
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blt jump1
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! CHECK: encoding: [0b1110110A,A,A,0x01'A']
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! CHECK-NEXT: fixup A - offset: 0, value: jump1, kind: FIXUP_LANAI_25
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! CHECK-NEXT: <MCInst #{{[0-9]+}} BRCC{{$}}
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! CHECK-NEXT: <MCOperand Expr:(jump1)>
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! CHECK-NEXT: <MCOperand Imm:13>
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bpl jump2
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! CHECK: encoding: [0b1110101A,A,A,A]
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! CHECK-NEXT: fixup A - offset: 0, value: jump2, kind: FIXUP_LANAI_25
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! CHECK-NEXT: <MCInst #{{[0-9]+}} BRCC{{$}}
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! CHECK-NEXT: <MCOperand Expr:(jump2)>
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! CHECK-NEXT: <MCOperand Imm:10>
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bt .
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! CHECK: .Ltmp{{[0-9]+}}
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! CHECK-NEXT: bt .Ltmp{{[0-9]+}}
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! CHECK: encoding: [0b1110000A,A,A,A]
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! CHECK-NEXT: fixup A - offset: 0, value: .Ltmp0, kind: FIXUP_LANAI_25
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! CHECK-NEXT: <MCInst #{{[0-9]+}} BT{{$}}
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! CHECK-NEXT: <MCOperand Expr:(.Ltmp0)>
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! SCC
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spl %r19
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! CHECK: encoding: [0xea,0x4c,0x00,0x02]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} SCC{{$}}
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! CHECK-NEXT: <MCOperand Reg:26>
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! CHECK-NEXT: <MCOperand Imm:10>
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! BRR
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bf.r 0x456
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! CHECK: encoding: [0xe1,0x00,0x04,0x57]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} BRR{{$}}
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! CHECK-NEXT: <MCOperand Imm:1110>
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! CHECK-NEXT: <MCOperand Imm:1>
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! Conditional ALU
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add.ge %r13, %r14, %r18
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! CHECK: encoding: [0xc9,0x34,0x70,0x06]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} ADD_R
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! CHECK-NEXT: <MCOperand Reg:25>
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! CHECK-NEXT: <MCOperand Reg:20>
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! CHECK-NEXT: <MCOperand Reg:21>
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! CHECK-NEXT: <MCOperand Imm:12>>
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add.f %r13, %r14, %r18
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! CHECK: encoding: [0xc9,0x36,0x70,0x00]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} ADD_F_R
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! CHECK-NEXT: <MCOperand Reg:25>
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! CHECK-NEXT: <MCOperand Reg:20>
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! CHECK-NEXT: <MCOperand Reg:21>
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! CHECK-NEXT: <MCOperand Imm:0>>
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@ -1,13 +1,13 @@
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// RUN: llvm-mc -triple lanai-unknown-unknown -show-encoding -o - %s | FileCheck %s
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! RUN: llvm-mc -triple lanai-unknown-unknown -show-encoding -o - < %s | FileCheck %s
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// CHECK: bt .Ltmp0 ! encoding: [0b1110000A,A,A,A]
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// CHECK-NEXT: ! fixup A - offset: 0, value: .Ltmp0, kind: FIXUP_LANAI_25
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! CHECK: bt .Ltmp0 ! encoding: [0b1110000A,A,A,A]
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! CHECK-NEXT: ! fixup A - offset: 0, value: .Ltmp0, kind: FIXUP_LANAI_25
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bt 1f
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nop
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1:
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// CHECK: bt foo ! encoding: [0b1110000A,A,A,A]
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// CHECK-NEXT: ! fixup A - offset: 0, value: foo, kind: FIXUP_LANAI_25
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! CHECK: bt foo ! encoding: [0b1110000A,A,A,A]
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! CHECK-NEXT: ! fixup A - offset: 0, value: foo, kind: FIXUP_LANAI_25
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bt foo
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nop
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@ -0,0 +1,247 @@
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! RUN: llvm-mc -arch=lanai -show-encoding -show-inst < %s | FileCheck %s
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! Checking the machine instructions generated from ASM instructions for ALU
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! operations.
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! RM class
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ld [%r7], %r6
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! CHECK: encoding: [0x83,0x1c,0x00,0x00]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
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! CHECK-NEXT: <MCOperand Reg:13>
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! CHECK-NEXT: <MCOperand Reg:14>
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! CHECK-NEXT: <MCOperand Imm:0>
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! CHECK-NEXT: <MCOperand Imm:0>
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ld [%r6], %r6
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! CHECK: encoding: [0x83,0x18,0x00,0x00]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
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! CHECK-NEXT: <MCOperand Reg:13>
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! CHECK-NEXT: <MCOperand Reg:13>
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! CHECK-NEXT: <MCOperand Imm:0>
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! CHECK-NEXT: <MCOperand Imm:0>
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st %r6, [%r7]
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! CHECK: encoding: [0x93,0x1c,0x00,0x00]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} SW_RI{{$}}
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! CHECK-NEXT: <MCOperand Reg:13>
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! CHECK-NEXT: <MCOperand Reg:14>
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! CHECK-NEXT: <MCOperand Imm:0>
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! CHECK-NEXT: <MCOperand Imm:0>
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ld 0x123[%r7*], %r6
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! CHECK: encoding: [0x83,0x1d,0x01,0x23]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
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! CHECK-NEXT: <MCOperand Reg:13>
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! CHECK-NEXT: <MCOperand Reg:14>
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! CHECK-NEXT: <MCOperand Imm:291>
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! CHECK-NEXT: <MCOperand Imm:128>
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ld [%r7--], %r6
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! CHECK: encoding: [0x83,0x1d,0xff,0xfc]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
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! CHECK-NEXT: <MCOperand Reg:13>
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! CHECK-NEXT: <MCOperand Reg:14>
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! CHECK-NEXT: <MCOperand Imm:-4>
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! CHECK-NEXT: <MCOperand Imm:128>
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ld 0x123[%r7], %r6
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! CHECK: encoding: [0x83,0x1e,0x01,0x23]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
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! CHECK-NEXT: <MCOperand Reg:13>
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! CHECK-NEXT: <MCOperand Reg:14>
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! CHECK-NEXT: <MCOperand Imm:291>
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! CHECK-NEXT: <MCOperand Imm:0>
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ld 0x123[*%r7], %r6
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! CHECK: encoding: [0x83,0x1f,0x01,0x23]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
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! CHECK-NEXT: <MCOperand Reg:13>
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! CHECK-NEXT: <MCOperand Reg:14>
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! CHECK-NEXT: <MCOperand Imm:291>
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! CHECK-NEXT: <MCOperand Imm:64>
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ld [--%r7], %r6
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! CHECK: encoding: [0x83,0x1f,0xff,0xfc]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
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! CHECK-NEXT: <MCOperand Reg:13>
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! CHECK-NEXT: <MCOperand Reg:14>
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! CHECK-NEXT: <MCOperand Imm:-4>
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! CHECK-NEXT: <MCOperand Imm:64>
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st %r6, [%r7++]
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! CHECK: encoding: [0x93,0x1d,0x00,0x04]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} SW_RI{{$}}
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! CHECK-NEXT: <MCOperand Reg:13>
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! CHECK-NEXT: <MCOperand Reg:14>
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! CHECK-NEXT: <MCOperand Imm:4>
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! CHECK-NEXT: <MCOperand Imm:128>
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st.h %r6, [%r7++]
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! CHECK: encoding: [0xf3,0x1f,0x24,0x02]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} STH_RI{{$}}
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! CHECK-NEXT: <MCOperand Reg:13>
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! CHECK-NEXT: <MCOperand Reg:14>
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! CHECK-NEXT: <MCOperand Imm:2>
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! CHECK-NEXT: <MCOperand Imm:128>>
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ld.b [--%r7], %r6
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! CHECK: encoding: [0xf3,0x1f,0x4f,0xff]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} LDBs_RI{{$}}
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! CHECK-NEXT: <MCOperand Reg:13>
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! CHECK-NEXT: <MCOperand Reg:14>
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! CHECK-NEXT: <MCOperand Imm:-1>
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! CHECK-NEXT: <MCOperand Imm:64>>
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! Largest RM value before SLS encoding is used
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ld [0x7fff], %r7
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! CHECK: encoding: [0x83,0x82,0x7f,0xff]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
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! CHECK-NEXT: <MCOperand Reg:14>
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! CHECK-NEXT: <MCOperand Reg:7>
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! CHECK-NEXT: <MCOperand Imm:32767>
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! CHECK-NEXT: <MCOperand Imm:0>
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ld [0x8000], %r7
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! CHECK: encoding: [0xf3,0x80,0x80,0x00]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} LDADDR{{$}}
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! CHECK-NEXT: <MCOperand Reg:14>
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! CHECK-NEXT: <MCOperand Imm:32768>
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! Negative RM value
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ld [0xfffffe8c], %pc
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! CHECK: encoding: [0x81,0x02,0xfe,0x8c]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
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! CHECK-NEXT: <MCOperand Reg:2>
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! CHECK-NEXT: <MCOperand Reg:7>
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! CHECK-NEXT: <MCOperand Imm:-372>
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! CHECK-NEXT: <MCOperand Imm:0>
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ld [-372], %pc
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! CHECK: encoding: [0x81,0x02,0xfe,0x8c]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
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! CHECK-NEXT: <MCOperand Reg:2>
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! CHECK-NEXT: <MCOperand Reg:7>
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! CHECK-NEXT: <MCOperand Imm:-372>
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! CHECK-NEXT: <MCOperand Imm:0>
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! RRM class
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ld %r9[%r12*], %r20
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! CHECK: encoding: [0xaa,0x31,0x48,0x02]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RR{{$}}
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! CHECK-NEXT: <MCOperand Reg:27>
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! CHECK-NEXT: <MCOperand Reg:19>
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! CHECK-NEXT: <MCOperand Reg:16>
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! CHECK-NEXT: <MCOperand Imm:128>
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ld %r9[%r12], %r20
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! CHECK: encoding: [0xaa,0x32,0x48,0x02]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RR{{$}}
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! CHECK-NEXT: <MCOperand Reg:27>
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! CHECK-NEXT: <MCOperand Reg:19>
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! CHECK-NEXT: <MCOperand Reg:16>
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! CHECK-NEXT: <MCOperand Imm:0>
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ld [%r12 sub %r9], %r20
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! CHECK: encoding: [0xaa,0x32,0x4a,0x02]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RR{{$}}
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! CHECK-NEXT: <MCOperand Reg:27>
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! CHECK-NEXT: <MCOperand Reg:19>
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! CHECK-NEXT: <MCOperand Reg:16>
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! CHECK-NEXT: <MCOperand Imm:2>
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ld %r9[*%r12], %r20
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! CHECK: encoding: [0xaa,0x33,0x48,0x02]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RR{{$}}
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! CHECK-NEXT: <MCOperand Reg:27>
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! CHECK-NEXT: <MCOperand Reg:19>
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! CHECK-NEXT: <MCOperand Reg:16>
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! CHECK-NEXT: <MCOperand Imm:64>
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st %r20, %r9[*%r12]
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! CHECK: encoding: [0xba,0x33,0x48,0x02]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} SW_RR{{$}}
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! CHECK-NEXT: <MCOperand Reg:27>
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! CHECK-NEXT: <MCOperand Reg:19>
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! CHECK-NEXT: <MCOperand Reg:16>
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! CHECK-NEXT: <MCOperand Imm:64>
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ld.b [%r12 sub %r9], %r20
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! CHECK: encoding: [0xaa,0x32,0x4a,0x04]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} LDBs_RR{{$}}
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! CHECK-NEXT: <MCOperand Reg:27>
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! CHECK-NEXT: <MCOperand Reg:19>
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! CHECK-NEXT: <MCOperand Reg:16>
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! CHECK-NEXT: <MCOperand Imm:2>
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uld.h [%r12 sub %r9], %r20
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! CHECK: encoding: [0xaa,0x32,0x4a,0x01]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} LDHz_RR{{$}}
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! CHECK-NEXT: <MCOperand Reg:27>
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! CHECK-NEXT: <MCOperand Reg:19>
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! CHECK-NEXT: <MCOperand Reg:16>
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! CHECK-NEXT: <MCOperand Imm:2>
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! SPLS class
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st.b %r3, [%r6]
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! CHECK: encoding: [0xf1,0x9b,0x60,0x00]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} STB_RI{{$}}
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! CHECK-NEXT: <MCOperand Reg:10>
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! CHECK-NEXT: <MCOperand Reg:13>
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! CHECK-NEXT: <MCOperand Imm:0>
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! CHECK-NEXT: <MCOperand Imm:0>
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st.b %r3, 1[%r6*]
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! CHECK: encoding: [0xf1,0x9b,0x64,0x01]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} STB_RI{{$}}
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! CHECK-NEXT: <MCOperand Reg:10>
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! CHECK-NEXT: <MCOperand Reg:13>
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! CHECK-NEXT: <MCOperand Imm:1>
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! CHECK-NEXT: <MCOperand Imm:128>
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st.b %r3, 1[%r6]
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! CHECK: encoding: [0xf1,0x9b,0x68,0x01]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} STB_RI{{$}}
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! CHECK-NEXT: <MCOperand Reg:10>
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! CHECK-NEXT: <MCOperand Reg:13>
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! CHECK-NEXT: <MCOperand Imm:1>
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! CHECK-NEXT: <MCOperand Imm:0>
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st.b %r3, 1[*%r6]
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! CHECK: encoding: [0xf1,0x9b,0x6c,0x01]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} STB_RI{{$}}
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! CHECK-NEXT: <MCOperand Reg:10>
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! CHECK-NEXT: <MCOperand Reg:13>
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! CHECK-NEXT: <MCOperand Imm:1>
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! CHECK-NEXT: <MCOperand Imm:64>
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! SLS class
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st %r30, [0x1234]
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! CHECK: encoding: [0xff,0x01,0x12,0x34]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} STADDR{{$}}
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! CHECK-NEXT: <MCOperand Reg:37>
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! CHECK-NEXT: <MCOperand Imm:4660>
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ld [0xfe8c], %pc
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! CHECK: encoding: [0xf1,0x00,0xfe,0x8c]
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! CHECK-NEXT: <MCInst #{{[0-9]+}} LDADDR{{$}}
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! CHECK-NEXT: <MCOperand Reg:2>
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! CHECK-NEXT: <MCOperand Imm:65164>
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! SLI class
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mov hi(x), %r4
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! CHECK: encoding: [0x02,0x01,A,A]
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! CHECK-NEXT: fixup A - offset: 0, value: hi(x), kind: FIXUP_LANAI_HI16{{$}}
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! CHECK-NEXT: <MCInst #{{[0-9]+}} ADD_I_HI
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! CHECK-NEXT: <MCOperand Reg:11>
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! CHECK-NEXT: <MCOperand Reg:7>
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! CHECK-NEXT: <MCOperand Expr:(hi(x))>
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mov hi(l+4), %r7
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! CHECK: encoding: [0x03,0x81,A,A]
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! CHECK-NEXT: fixup A - offset: 0, value: (hi(l))+4, kind: FIXUP_LANAI_HI16{{$}}
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! CHECK-NEXT: <MCInst #{{[0-9]+}} ADD_I_HI
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! CHECK-NEXT: <MCOperand Reg:14>
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! CHECK-NEXT: <MCOperand Reg:7>
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! CHECK-NEXT: <MCOperand Expr:((hi(l))+4)>
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@ -840,3 +840,37 @@ spl %r19
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! CHECK: 0xea,0x4c,0x00,0x02
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bt 0x1234
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! CHECK: 0xe0,0x00,0x12,0x34
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sel.t %r9, %r15, %r12
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! CHECK: 0xc6,0x24,0x7f,0x00
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sel.f %r9, %r15, %r12
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! CHECK: 0xc6,0x25,0x7f,0x00
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sel.ugt %r9, %r15, %r12
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! CHECK: 0xc6,0x24,0x7f,0x01
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sel.ule %r9, %r15, %r12
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! CHECK: 0xc6,0x25,0x7f,0x01
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sel.ult %r9, %r15, %r12
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! CHECK: 0xc6,0x24,0x7f,0x02
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sel.uge %r9, %r15, %r12
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! CHECK: 0xc6,0x25,0x7f,0x02
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sel.ne %r9, %r15, %r12
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! CHECK: 0xc6,0x24,0x7f,0x03
|
||||
sel.eq %r9, %r15, %r12
|
||||
! CHECK: 0xc6,0x25,0x7f,0x03
|
||||
sel.vc %r9, %r15, %r12
|
||||
! CHECK: 0xc6,0x24,0x7f,0x04
|
||||
sel.vs %r9, %r15, %r12
|
||||
! CHECK: 0xc6,0x25,0x7f,0x04
|
||||
sel.pl %r9, %r15, %r12
|
||||
! CHECK: 0xc6,0x24,0x7f,0x05
|
||||
sel.mi %r9, %r15, %r12
|
||||
! CHECK: 0xc6,0x25,0x7f,0x05
|
||||
sel.ge %r9, %r15, %r12
|
||||
! CHECK: 0xc6,0x24,0x7f,0x06
|
||||
sel.lt %r9, %r15, %r12
|
||||
! CHECK: 0xc6,0x25,0x7f,0x06
|
||||
sel.gt %r9, %r15, %r12
|
||||
! CHECK: 0xc6,0x24,0x7f,0x07
|
||||
sel.le %r9, %r15, %r12
|
||||
! CHECK: 0xc6,0x25,0x7f,0x07
|
||||
trailz %r15, %r12
|
||||
! CHECK: 0xd6,0x3c,0x00,0x03
|
||||
|
|
|
|||
Loading…
Reference in New Issue