forked from OSchip/llvm-project
[NFC][CodeGen][X86][AArch64] Add tests for C++ std::midpoint() pattern (PR40965)
Tests only for integers, not floating point or pointers. The scalar 8-bit case uses branch instead of CMOV, because there is no no 8-bit CMOV. Vector tests are for consistency, since it can be vectorized. https://bugs.llvm.org/show_bug.cgi?id=40965 llvm-svn: 355436
This commit is contained in:
Roman Lebedev
parent
14c1e08ff5
commit
c38831e11d
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@ -0,0 +1,535 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
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; These test cases are inspired by C++2a std::midpoint().
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; See https://bugs.llvm.org/show_bug.cgi?id=40965
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; ---------------------------------------------------------------------------- ;
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; 32-bit width
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; ---------------------------------------------------------------------------- ;
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; Values come from regs
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define i32 @scalar_i32_signed_reg_reg(i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: scalar_i32_signed_reg_reg:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp w0, w1
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; CHECK-NEXT: csel w9, w1, w0, gt
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; CHECK-NEXT: csel w10, w0, w1, gt
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; CHECK-NEXT: mov w8, #-1
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; CHECK-NEXT: sub w9, w10, w9
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; CHECK-NEXT: cneg w8, w8, le
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; CHECK-NEXT: lsr w9, w9, #1
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; CHECK-NEXT: madd w0, w9, w8, w0
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; CHECK-NEXT: ret
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%t3 = icmp sgt i32 %a1, %a2 ; signed
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%t4 = select i1 %t3, i32 -1, i32 1
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%t5 = select i1 %t3, i32 %a2, i32 %a1
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%t6 = select i1 %t3, i32 %a1, i32 %a2
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%t7 = sub i32 %t6, %t5
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%t8 = lshr i32 %t7, 1
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%t9 = mul nsw i32 %t8, %t4 ; signed
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%a10 = add nsw i32 %t9, %a1 ; signed
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ret i32 %a10
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}
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define i32 @scalar_i32_unsigned_reg_reg(i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: scalar_i32_unsigned_reg_reg:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp w0, w1
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; CHECK-NEXT: csel w9, w1, w0, hi
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; CHECK-NEXT: csel w10, w0, w1, hi
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; CHECK-NEXT: mov w8, #-1
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; CHECK-NEXT: sub w9, w10, w9
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; CHECK-NEXT: cneg w8, w8, ls
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; CHECK-NEXT: lsr w9, w9, #1
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; CHECK-NEXT: madd w0, w9, w8, w0
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; CHECK-NEXT: ret
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%t3 = icmp ugt i32 %a1, %a2
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%t4 = select i1 %t3, i32 -1, i32 1
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%t5 = select i1 %t3, i32 %a2, i32 %a1
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%t6 = select i1 %t3, i32 %a1, i32 %a2
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%t7 = sub i32 %t6, %t5
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%t8 = lshr i32 %t7, 1
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%t9 = mul i32 %t8, %t4
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%a10 = add i32 %t9, %a1
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ret i32 %a10
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}
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; Values are loaded. Only check signed case.
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define i32 @scalar_i32_signed_mem_reg(i32* %a1_addr, i32 %a2) nounwind {
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; CHECK-LABEL: scalar_i32_signed_mem_reg:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr w8, [x0]
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; CHECK-NEXT: mov w9, #-1
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; CHECK-NEXT: cmp w8, w1
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; CHECK-NEXT: csel w10, w1, w8, gt
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; CHECK-NEXT: csel w11, w8, w1, gt
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; CHECK-NEXT: sub w10, w11, w10
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; CHECK-NEXT: cneg w9, w9, le
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; CHECK-NEXT: lsr w10, w10, #1
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; CHECK-NEXT: madd w0, w10, w9, w8
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; CHECK-NEXT: ret
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%a1 = load i32, i32* %a1_addr
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%t3 = icmp sgt i32 %a1, %a2 ; signed
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%t4 = select i1 %t3, i32 -1, i32 1
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%t5 = select i1 %t3, i32 %a2, i32 %a1
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%t6 = select i1 %t3, i32 %a1, i32 %a2
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%t7 = sub i32 %t6, %t5
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%t8 = lshr i32 %t7, 1
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%t9 = mul nsw i32 %t8, %t4 ; signed
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%a10 = add nsw i32 %t9, %a1 ; signed
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ret i32 %a10
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}
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define i32 @scalar_i32_signed_reg_mem(i32 %a1, i32* %a2_addr) nounwind {
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; CHECK-LABEL: scalar_i32_signed_reg_mem:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr w8, [x1]
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; CHECK-NEXT: mov w9, #-1
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; CHECK-NEXT: cmp w0, w8
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; CHECK-NEXT: csel w10, w8, w0, gt
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; CHECK-NEXT: csel w8, w0, w8, gt
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; CHECK-NEXT: sub w8, w8, w10
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; CHECK-NEXT: cneg w9, w9, le
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; CHECK-NEXT: lsr w8, w8, #1
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; CHECK-NEXT: madd w0, w8, w9, w0
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; CHECK-NEXT: ret
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%a2 = load i32, i32* %a2_addr
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%t3 = icmp sgt i32 %a1, %a2 ; signed
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%t4 = select i1 %t3, i32 -1, i32 1
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%t5 = select i1 %t3, i32 %a2, i32 %a1
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%t6 = select i1 %t3, i32 %a1, i32 %a2
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%t7 = sub i32 %t6, %t5
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%t8 = lshr i32 %t7, 1
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%t9 = mul nsw i32 %t8, %t4 ; signed
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%a10 = add nsw i32 %t9, %a1 ; signed
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ret i32 %a10
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}
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define i32 @scalar_i32_signed_mem_mem(i32* %a1_addr, i32* %a2_addr) nounwind {
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; CHECK-LABEL: scalar_i32_signed_mem_mem:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr w8, [x0]
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; CHECK-NEXT: ldr w9, [x1]
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; CHECK-NEXT: mov w10, #-1
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; CHECK-NEXT: cmp w8, w9
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; CHECK-NEXT: csel w11, w9, w8, gt
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; CHECK-NEXT: csel w9, w8, w9, gt
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; CHECK-NEXT: sub w9, w9, w11
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; CHECK-NEXT: cneg w10, w10, le
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; CHECK-NEXT: lsr w9, w9, #1
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; CHECK-NEXT: madd w0, w9, w10, w8
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; CHECK-NEXT: ret
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%a1 = load i32, i32* %a1_addr
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%a2 = load i32, i32* %a2_addr
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%t3 = icmp sgt i32 %a1, %a2 ; signed
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%t4 = select i1 %t3, i32 -1, i32 1
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%t5 = select i1 %t3, i32 %a2, i32 %a1
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%t6 = select i1 %t3, i32 %a1, i32 %a2
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%t7 = sub i32 %t6, %t5
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%t8 = lshr i32 %t7, 1
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%t9 = mul nsw i32 %t8, %t4 ; signed
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%a10 = add nsw i32 %t9, %a1 ; signed
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ret i32 %a10
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}
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; ---------------------------------------------------------------------------- ;
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; 64-bit width
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; ---------------------------------------------------------------------------- ;
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; Values come from regs
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define i64 @scalar_i64_signed_reg_reg(i64 %a1, i64 %a2) nounwind {
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; CHECK-LABEL: scalar_i64_signed_reg_reg:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, x1
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; CHECK-NEXT: csel x9, x1, x0, gt
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; CHECK-NEXT: csel x10, x0, x1, gt
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; CHECK-NEXT: mov x8, #-1
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; CHECK-NEXT: sub x9, x10, x9
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; CHECK-NEXT: cneg x8, x8, le
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; CHECK-NEXT: lsr x9, x9, #1
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; CHECK-NEXT: madd x0, x9, x8, x0
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; CHECK-NEXT: ret
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%t3 = icmp sgt i64 %a1, %a2 ; signed
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%t4 = select i1 %t3, i64 -1, i64 1
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%t5 = select i1 %t3, i64 %a2, i64 %a1
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%t6 = select i1 %t3, i64 %a1, i64 %a2
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%t7 = sub i64 %t6, %t5
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%t8 = lshr i64 %t7, 1
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%t9 = mul nsw i64 %t8, %t4 ; signed
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%a10 = add nsw i64 %t9, %a1 ; signed
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ret i64 %a10
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}
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define i64 @scalar_i64_unsigned_reg_reg(i64 %a1, i64 %a2) nounwind {
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; CHECK-LABEL: scalar_i64_unsigned_reg_reg:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, x1
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; CHECK-NEXT: csel x9, x1, x0, hi
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; CHECK-NEXT: csel x10, x0, x1, hi
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; CHECK-NEXT: mov x8, #-1
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; CHECK-NEXT: sub x9, x10, x9
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; CHECK-NEXT: cneg x8, x8, ls
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; CHECK-NEXT: lsr x9, x9, #1
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; CHECK-NEXT: madd x0, x9, x8, x0
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; CHECK-NEXT: ret
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%t3 = icmp ugt i64 %a1, %a2
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%t4 = select i1 %t3, i64 -1, i64 1
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%t5 = select i1 %t3, i64 %a2, i64 %a1
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%t6 = select i1 %t3, i64 %a1, i64 %a2
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%t7 = sub i64 %t6, %t5
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%t8 = lshr i64 %t7, 1
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%t9 = mul i64 %t8, %t4
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%a10 = add i64 %t9, %a1
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ret i64 %a10
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}
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; Values are loaded. Only check signed case.
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define i64 @scalar_i64_signed_mem_reg(i64* %a1_addr, i64 %a2) nounwind {
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; CHECK-LABEL: scalar_i64_signed_mem_reg:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr x8, [x0]
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; CHECK-NEXT: mov x9, #-1
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; CHECK-NEXT: cmp x8, x1
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; CHECK-NEXT: csel x10, x1, x8, gt
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; CHECK-NEXT: csel x11, x8, x1, gt
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; CHECK-NEXT: sub x10, x11, x10
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; CHECK-NEXT: cneg x9, x9, le
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; CHECK-NEXT: lsr x10, x10, #1
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; CHECK-NEXT: madd x0, x10, x9, x8
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; CHECK-NEXT: ret
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%a1 = load i64, i64* %a1_addr
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%t3 = icmp sgt i64 %a1, %a2 ; signed
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%t4 = select i1 %t3, i64 -1, i64 1
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%t5 = select i1 %t3, i64 %a2, i64 %a1
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%t6 = select i1 %t3, i64 %a1, i64 %a2
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%t7 = sub i64 %t6, %t5
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%t8 = lshr i64 %t7, 1
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%t9 = mul nsw i64 %t8, %t4 ; signed
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%a10 = add nsw i64 %t9, %a1 ; signed
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ret i64 %a10
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}
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define i64 @scalar_i64_signed_reg_mem(i64 %a1, i64* %a2_addr) nounwind {
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; CHECK-LABEL: scalar_i64_signed_reg_mem:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr x8, [x1]
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; CHECK-NEXT: mov x9, #-1
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; CHECK-NEXT: cmp x0, x8
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; CHECK-NEXT: csel x10, x8, x0, gt
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; CHECK-NEXT: csel x8, x0, x8, gt
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; CHECK-NEXT: sub x8, x8, x10
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; CHECK-NEXT: cneg x9, x9, le
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; CHECK-NEXT: lsr x8, x8, #1
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; CHECK-NEXT: madd x0, x8, x9, x0
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; CHECK-NEXT: ret
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%a2 = load i64, i64* %a2_addr
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%t3 = icmp sgt i64 %a1, %a2 ; signed
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%t4 = select i1 %t3, i64 -1, i64 1
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%t5 = select i1 %t3, i64 %a2, i64 %a1
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%t6 = select i1 %t3, i64 %a1, i64 %a2
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%t7 = sub i64 %t6, %t5
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%t8 = lshr i64 %t7, 1
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%t9 = mul nsw i64 %t8, %t4 ; signed
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%a10 = add nsw i64 %t9, %a1 ; signed
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ret i64 %a10
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}
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define i64 @scalar_i64_signed_mem_mem(i64* %a1_addr, i64* %a2_addr) nounwind {
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; CHECK-LABEL: scalar_i64_signed_mem_mem:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr x8, [x0]
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; CHECK-NEXT: ldr x9, [x1]
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; CHECK-NEXT: mov x10, #-1
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; CHECK-NEXT: cmp x8, x9
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; CHECK-NEXT: csel x11, x9, x8, gt
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; CHECK-NEXT: csel x9, x8, x9, gt
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; CHECK-NEXT: sub x9, x9, x11
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; CHECK-NEXT: cneg x10, x10, le
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; CHECK-NEXT: lsr x9, x9, #1
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; CHECK-NEXT: madd x0, x9, x10, x8
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; CHECK-NEXT: ret
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%a1 = load i64, i64* %a1_addr
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%a2 = load i64, i64* %a2_addr
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%t3 = icmp sgt i64 %a1, %a2 ; signed
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%t4 = select i1 %t3, i64 -1, i64 1
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%t5 = select i1 %t3, i64 %a2, i64 %a1
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%t6 = select i1 %t3, i64 %a1, i64 %a2
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%t7 = sub i64 %t6, %t5
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%t8 = lshr i64 %t7, 1
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%t9 = mul nsw i64 %t8, %t4 ; signed
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%a10 = add nsw i64 %t9, %a1 ; signed
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ret i64 %a10
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}
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; ---------------------------------------------------------------------------- ;
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; 16-bit width
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; ---------------------------------------------------------------------------- ;
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; Values come from regs
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define i16 @scalar_i16_signed_reg_reg(i16 %a1, i16 %a2) nounwind {
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; CHECK-LABEL: scalar_i16_signed_reg_reg:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sxth w8, w0
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; CHECK-NEXT: mov w9, #-1
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; CHECK-NEXT: cmp w8, w1, sxth
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; CHECK-NEXT: cneg w8, w9, le
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; CHECK-NEXT: csel w9, w1, w0, gt
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; CHECK-NEXT: csel w10, w0, w1, gt
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; CHECK-NEXT: sub w9, w10, w9
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; CHECK-NEXT: ubfx w9, w9, #1, #15
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; CHECK-NEXT: madd w0, w9, w8, w0
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; CHECK-NEXT: ret
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%t3 = icmp sgt i16 %a1, %a2 ; signed
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%t4 = select i1 %t3, i16 -1, i16 1
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%t5 = select i1 %t3, i16 %a2, i16 %a1
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%t6 = select i1 %t3, i16 %a1, i16 %a2
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%t7 = sub i16 %t6, %t5
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%t8 = lshr i16 %t7, 1
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%t9 = mul nsw i16 %t8, %t4 ; signed
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%a10 = add nsw i16 %t9, %a1 ; signed
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ret i16 %a10
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}
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define i16 @scalar_i16_unsigned_reg_reg(i16 %a1, i16 %a2) nounwind {
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; CHECK-LABEL: scalar_i16_unsigned_reg_reg:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w0, #0xffff
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; CHECK-NEXT: mov w9, #-1
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; CHECK-NEXT: cmp w8, w1, uxth
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; CHECK-NEXT: cneg w8, w9, ls
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; CHECK-NEXT: csel w9, w1, w0, hi
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; CHECK-NEXT: csel w10, w0, w1, hi
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; CHECK-NEXT: sub w9, w10, w9
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; CHECK-NEXT: ubfx w9, w9, #1, #15
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; CHECK-NEXT: madd w0, w9, w8, w0
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; CHECK-NEXT: ret
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%t3 = icmp ugt i16 %a1, %a2
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%t4 = select i1 %t3, i16 -1, i16 1
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%t5 = select i1 %t3, i16 %a2, i16 %a1
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%t6 = select i1 %t3, i16 %a1, i16 %a2
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%t7 = sub i16 %t6, %t5
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%t8 = lshr i16 %t7, 1
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%t9 = mul i16 %t8, %t4
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%a10 = add i16 %t9, %a1
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ret i16 %a10
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}
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; Values are loaded. Only check signed case.
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define i16 @scalar_i16_signed_mem_reg(i16* %a1_addr, i16 %a2) nounwind {
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; CHECK-LABEL: scalar_i16_signed_mem_reg:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldrsh w8, [x0]
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; CHECK-NEXT: mov w9, #-1
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; CHECK-NEXT: cmp w8, w1, sxth
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; CHECK-NEXT: csel w10, w1, w8, gt
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; CHECK-NEXT: csel w11, w8, w1, gt
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; CHECK-NEXT: sub w10, w11, w10
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; CHECK-NEXT: cneg w9, w9, le
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; CHECK-NEXT: ubfx w10, w10, #1, #15
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; CHECK-NEXT: madd w0, w10, w9, w8
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; CHECK-NEXT: ret
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%a1 = load i16, i16* %a1_addr
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%t3 = icmp sgt i16 %a1, %a2 ; signed
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%t4 = select i1 %t3, i16 -1, i16 1
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%t5 = select i1 %t3, i16 %a2, i16 %a1
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%t6 = select i1 %t3, i16 %a1, i16 %a2
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%t7 = sub i16 %t6, %t5
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%t8 = lshr i16 %t7, 1
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%t9 = mul nsw i16 %t8, %t4 ; signed
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%a10 = add nsw i16 %t9, %a1 ; signed
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ret i16 %a10
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}
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define i16 @scalar_i16_signed_reg_mem(i16 %a1, i16* %a2_addr) nounwind {
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; CHECK-LABEL: scalar_i16_signed_reg_mem:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldrsh w8, [x1]
|
||||
; CHECK-NEXT: sxth w9, w0
|
||||
; CHECK-NEXT: mov w10, #-1
|
||||
; CHECK-NEXT: cmp w9, w8
|
||||
; CHECK-NEXT: cneg w9, w10, le
|
||||
; CHECK-NEXT: csel w10, w8, w0, gt
|
||||
; CHECK-NEXT: csel w8, w0, w8, gt
|
||||
; CHECK-NEXT: sub w8, w8, w10
|
||||
; CHECK-NEXT: ubfx w8, w8, #1, #15
|
||||
; CHECK-NEXT: madd w0, w8, w9, w0
|
||||
; CHECK-NEXT: ret
|
||||
%a2 = load i16, i16* %a2_addr
|
||||
%t3 = icmp sgt i16 %a1, %a2 ; signed
|
||||
%t4 = select i1 %t3, i16 -1, i16 1
|
||||
%t5 = select i1 %t3, i16 %a2, i16 %a1
|
||||
%t6 = select i1 %t3, i16 %a1, i16 %a2
|
||||
%t7 = sub i16 %t6, %t5
|
||||
%t8 = lshr i16 %t7, 1
|
||||
%t9 = mul nsw i16 %t8, %t4 ; signed
|
||||
%a10 = add nsw i16 %t9, %a1 ; signed
|
||||
ret i16 %a10
|
||||
}
|
||||
|
||||
define i16 @scalar_i16_signed_mem_mem(i16* %a1_addr, i16* %a2_addr) nounwind {
|
||||
; CHECK-LABEL: scalar_i16_signed_mem_mem:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldrsh w8, [x0]
|
||||
; CHECK-NEXT: ldrsh w9, [x1]
|
||||
; CHECK-NEXT: mov w10, #-1
|
||||
; CHECK-NEXT: cmp w8, w9
|
||||
; CHECK-NEXT: csel w11, w9, w8, gt
|
||||
; CHECK-NEXT: csel w9, w8, w9, gt
|
||||
; CHECK-NEXT: sub w9, w9, w11
|
||||
; CHECK-NEXT: cneg w10, w10, le
|
||||
; CHECK-NEXT: ubfx w9, w9, #1, #15
|
||||
; CHECK-NEXT: madd w0, w9, w10, w8
|
||||
; CHECK-NEXT: ret
|
||||
%a1 = load i16, i16* %a1_addr
|
||||
%a2 = load i16, i16* %a2_addr
|
||||
%t3 = icmp sgt i16 %a1, %a2 ; signed
|
||||
%t4 = select i1 %t3, i16 -1, i16 1
|
||||
%t5 = select i1 %t3, i16 %a2, i16 %a1
|
||||
%t6 = select i1 %t3, i16 %a1, i16 %a2
|
||||
%t7 = sub i16 %t6, %t5
|
||||
%t8 = lshr i16 %t7, 1
|
||||
%t9 = mul nsw i16 %t8, %t4 ; signed
|
||||
%a10 = add nsw i16 %t9, %a1 ; signed
|
||||
ret i16 %a10
|
||||
}
|
||||
|
||||
; ---------------------------------------------------------------------------- ;
|
||||
; 8-bit width
|
||||
; ---------------------------------------------------------------------------- ;
|
||||
|
||||
; Values come from regs
|
||||
|
||||
define i8 @scalar_i8_signed_reg_reg(i8 %a1, i8 %a2) nounwind {
|
||||
; CHECK-LABEL: scalar_i8_signed_reg_reg:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: sxtb w8, w0
|
||||
; CHECK-NEXT: mov w9, #-1
|
||||
; CHECK-NEXT: cmp w8, w1, sxtb
|
||||
; CHECK-NEXT: cneg w8, w9, le
|
||||
; CHECK-NEXT: csel w9, w1, w0, gt
|
||||
; CHECK-NEXT: csel w10, w0, w1, gt
|
||||
; CHECK-NEXT: sub w9, w10, w9
|
||||
; CHECK-NEXT: ubfx w9, w9, #1, #7
|
||||
; CHECK-NEXT: madd w0, w9, w8, w0
|
||||
; CHECK-NEXT: ret
|
||||
%t3 = icmp sgt i8 %a1, %a2 ; signed
|
||||
%t4 = select i1 %t3, i8 -1, i8 1
|
||||
%t5 = select i1 %t3, i8 %a2, i8 %a1
|
||||
%t6 = select i1 %t3, i8 %a1, i8 %a2
|
||||
%t7 = sub i8 %t6, %t5
|
||||
%t8 = lshr i8 %t7, 1
|
||||
%t9 = mul nsw i8 %t8, %t4 ; signed
|
||||
%a10 = add nsw i8 %t9, %a1 ; signed
|
||||
ret i8 %a10
|
||||
}
|
||||
|
||||
define i8 @scalar_i8_unsigned_reg_reg(i8 %a1, i8 %a2) nounwind {
|
||||
; CHECK-LABEL: scalar_i8_unsigned_reg_reg:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: and w8, w0, #0xff
|
||||
; CHECK-NEXT: mov w9, #-1
|
||||
; CHECK-NEXT: cmp w8, w1, uxtb
|
||||
; CHECK-NEXT: cneg w8, w9, ls
|
||||
; CHECK-NEXT: csel w9, w1, w0, hi
|
||||
; CHECK-NEXT: csel w10, w0, w1, hi
|
||||
; CHECK-NEXT: sub w9, w10, w9
|
||||
; CHECK-NEXT: ubfx w9, w9, #1, #7
|
||||
; CHECK-NEXT: madd w0, w9, w8, w0
|
||||
; CHECK-NEXT: ret
|
||||
%t3 = icmp ugt i8 %a1, %a2
|
||||
%t4 = select i1 %t3, i8 -1, i8 1
|
||||
%t5 = select i1 %t3, i8 %a2, i8 %a1
|
||||
%t6 = select i1 %t3, i8 %a1, i8 %a2
|
||||
%t7 = sub i8 %t6, %t5
|
||||
%t8 = lshr i8 %t7, 1
|
||||
%t9 = mul i8 %t8, %t4
|
||||
%a10 = add i8 %t9, %a1
|
||||
ret i8 %a10
|
||||
}
|
||||
|
||||
; Values are loaded. Only check signed case.
|
||||
|
||||
define i8 @scalar_i8_signed_mem_reg(i8* %a1_addr, i8 %a2) nounwind {
|
||||
; CHECK-LABEL: scalar_i8_signed_mem_reg:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldrsb w8, [x0]
|
||||
; CHECK-NEXT: mov w9, #-1
|
||||
; CHECK-NEXT: cmp w8, w1, sxtb
|
||||
; CHECK-NEXT: csel w10, w1, w8, gt
|
||||
; CHECK-NEXT: csel w11, w8, w1, gt
|
||||
; CHECK-NEXT: sub w10, w11, w10
|
||||
; CHECK-NEXT: cneg w9, w9, le
|
||||
; CHECK-NEXT: ubfx w10, w10, #1, #7
|
||||
; CHECK-NEXT: madd w0, w10, w9, w8
|
||||
; CHECK-NEXT: ret
|
||||
%a1 = load i8, i8* %a1_addr
|
||||
%t3 = icmp sgt i8 %a1, %a2 ; signed
|
||||
%t4 = select i1 %t3, i8 -1, i8 1
|
||||
%t5 = select i1 %t3, i8 %a2, i8 %a1
|
||||
%t6 = select i1 %t3, i8 %a1, i8 %a2
|
||||
%t7 = sub i8 %t6, %t5
|
||||
%t8 = lshr i8 %t7, 1
|
||||
%t9 = mul nsw i8 %t8, %t4 ; signed
|
||||
%a10 = add nsw i8 %t9, %a1 ; signed
|
||||
ret i8 %a10
|
||||
}
|
||||
|
||||
define i8 @scalar_i8_signed_reg_mem(i8 %a1, i8* %a2_addr) nounwind {
|
||||
; CHECK-LABEL: scalar_i8_signed_reg_mem:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldrsb w8, [x1]
|
||||
; CHECK-NEXT: sxtb w9, w0
|
||||
; CHECK-NEXT: mov w10, #-1
|
||||
; CHECK-NEXT: cmp w9, w8
|
||||
; CHECK-NEXT: cneg w9, w10, le
|
||||
; CHECK-NEXT: csel w10, w8, w0, gt
|
||||
; CHECK-NEXT: csel w8, w0, w8, gt
|
||||
; CHECK-NEXT: sub w8, w8, w10
|
||||
; CHECK-NEXT: ubfx w8, w8, #1, #7
|
||||
; CHECK-NEXT: madd w0, w8, w9, w0
|
||||
; CHECK-NEXT: ret
|
||||
%a2 = load i8, i8* %a2_addr
|
||||
%t3 = icmp sgt i8 %a1, %a2 ; signed
|
||||
%t4 = select i1 %t3, i8 -1, i8 1
|
||||
%t5 = select i1 %t3, i8 %a2, i8 %a1
|
||||
%t6 = select i1 %t3, i8 %a1, i8 %a2
|
||||
%t7 = sub i8 %t6, %t5
|
||||
%t8 = lshr i8 %t7, 1
|
||||
%t9 = mul nsw i8 %t8, %t4 ; signed
|
||||
%a10 = add nsw i8 %t9, %a1 ; signed
|
||||
ret i8 %a10
|
||||
}
|
||||
|
||||
define i8 @scalar_i8_signed_mem_mem(i8* %a1_addr, i8* %a2_addr) nounwind {
|
||||
; CHECK-LABEL: scalar_i8_signed_mem_mem:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldrsb w8, [x0]
|
||||
; CHECK-NEXT: ldrsb w9, [x1]
|
||||
; CHECK-NEXT: mov w10, #-1
|
||||
; CHECK-NEXT: cmp w8, w9
|
||||
; CHECK-NEXT: csel w11, w9, w8, gt
|
||||
; CHECK-NEXT: csel w9, w8, w9, gt
|
||||
; CHECK-NEXT: sub w9, w9, w11
|
||||
; CHECK-NEXT: cneg w10, w10, le
|
||||
; CHECK-NEXT: ubfx w9, w9, #1, #7
|
||||
; CHECK-NEXT: madd w0, w9, w10, w8
|
||||
; CHECK-NEXT: ret
|
||||
%a1 = load i8, i8* %a1_addr
|
||||
%a2 = load i8, i8* %a2_addr
|
||||
%t3 = icmp sgt i8 %a1, %a2 ; signed
|
||||
%t4 = select i1 %t3, i8 -1, i8 1
|
||||
%t5 = select i1 %t3, i8 %a2, i8 %a1
|
||||
%t6 = select i1 %t3, i8 %a1, i8 %a2
|
||||
%t7 = sub i8 %t6, %t5
|
||||
%t8 = lshr i8 %t7, 1
|
||||
%t9 = mul nsw i8 %t8, %t4 ; signed
|
||||
%a10 = add nsw i8 %t9, %a1 ; signed
|
||||
ret i8 %a10
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue