forked from OSchip/llvm-project
SPARC backend: Modified LowerCall and LowerFormalArguments so that they use CallingConv assignments.
llvm-svn: 123749
This commit is contained in:
Venkatraman Govindaraju
parent
dfc547d181
commit
c386f8a1f6
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@ -24,9 +24,11 @@ def RetCC_Sparc32 : CallingConv<[
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// Sparc 32-bit C Calling convention.
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def CC_Sparc32 : CallingConv<[
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// All arguments get passed in integer registers if there is space.
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CCIfType<[i32, f32, f64], CCAssignToReg<[I0, I1, I2, I3, I4, I5]>>,
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// i32 f32 arguments get passed in integer registers if there is space.
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CCIfType<[i32, f32], CCAssignToReg<[I0, I1, I2, I3, I4, I5]>>,
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// f64 arguments are split and passed through registers or through stack.
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CCIfType<[f64], CCCustom<"CC_Sparc_Assign_f64">>,
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// Alternatively, they are assigned to the stack in 4-byte aligned units.
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CCAssignToStack<4, 4>
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]>;
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@ -33,6 +33,34 @@ using namespace llvm;
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// Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT,
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MVT &LocVT, CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags, CCState &State)
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{
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static const unsigned RegList[] = {
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SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
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};
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//Try to get first reg
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if (unsigned Reg = State.AllocateReg(RegList, 6)) {
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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} else {
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//Assign whole thing in stack
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State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
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State.AllocateStack(8,4),
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LocVT, LocInfo));
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return true;
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}
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//Try to get second reg
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if (unsigned Reg = State.AllocateReg(RegList, 6))
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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else
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State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
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State.AllocateStack(4,4),
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LocVT, LocInfo));
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return true;
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}
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#include "SparcGenCallingConv.inc"
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SDValue
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@ -101,136 +129,136 @@ SparcTargetLowering::LowerFormalArguments(SDValue Chain,
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ArgLocs, *DAG.getContext());
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CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
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static const unsigned ArgRegs[] = {
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SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
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};
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const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
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unsigned ArgOffset = 68;
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const unsigned StackOffset = 92;
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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SDValue ArgValue;
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CCValAssign &VA = ArgLocs[i];
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// FIXME: We ignore the register assignments of AnalyzeFormalArguments
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// because it doesn't know how to split a double into two i32 registers.
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EVT ObjectVT = VA.getValVT();
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switch (ObjectVT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("Unhandled argument type!");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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if (!Ins[i].Used) { // Argument is dead.
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if (CurArgReg < ArgRegEnd) ++CurArgReg;
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InVals.push_back(DAG.getUNDEF(ObjectVT));
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} else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
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unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
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MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
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SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
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if (ObjectVT != MVT::i32) {
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unsigned AssertOp = ISD::AssertSext;
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Arg = DAG.getNode(AssertOp, dl, MVT::i32, Arg,
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DAG.getValueType(ObjectVT));
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Arg = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Arg);
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}
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InVals.push_back(Arg);
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} else {
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
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true);
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SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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SDValue Load;
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if (ObjectVT == MVT::i32) {
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Load = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo(),
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false, false, 0);
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} else {
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ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
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// Sparc is big endian, so add an offset based on the ObjectVT.
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unsigned Offset = 4-std::max(1U, ObjectVT.getSizeInBits()/8);
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FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
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DAG.getConstant(Offset, MVT::i32));
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Load = DAG.getExtLoad(LoadOp, MVT::i32, dl, Chain, FIPtr,
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MachinePointerInfo(), ObjectVT, false, false,0);
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Load = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Load);
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}
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InVals.push_back(Load);
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}
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if (VA.isRegLoc()) {
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EVT RegVT = VA.getLocVT();
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ArgOffset += 4;
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break;
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case MVT::f32:
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if (!Ins[i].Used) { // Argument is dead.
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if (CurArgReg < ArgRegEnd) ++CurArgReg;
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InVals.push_back(DAG.getUNDEF(ObjectVT));
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} else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
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// FP value is passed in an integer register.
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unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
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MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
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SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
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if (VA.needsCustom()) {
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assert(VA.getLocVT() == MVT::f64);
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unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
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MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
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SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
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Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
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InVals.push_back(Arg);
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} else {
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
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true);
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SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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SDValue Load = DAG.getLoad(MVT::f32, dl, Chain, FIPtr,
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MachinePointerInfo(),
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false, false, 0);
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InVals.push_back(Load);
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}
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ArgOffset += 4;
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break;
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case MVT::i64:
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case MVT::f64:
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if (!Ins[i].Used) { // Argument is dead.
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if (CurArgReg < ArgRegEnd) ++CurArgReg;
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if (CurArgReg < ArgRegEnd) ++CurArgReg;
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InVals.push_back(DAG.getUNDEF(ObjectVT));
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} else {
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SDValue HiVal;
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if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
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unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
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MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
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HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
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} else {
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
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true);
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SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo(),
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false, false, 0);
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}
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assert(i+1 < e);
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CCValAssign &NextVA = ArgLocs[++i];
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SDValue LoVal;
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if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
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unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
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MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
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LoVal = DAG.getCopyFromReg(Chain, dl, VRegLo, MVT::i32);
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} else {
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4,
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true);
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if (NextVA.isMemLoc()) {
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int FrameIdx = MF.getFrameInfo()->
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CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
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SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo(),
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LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
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MachinePointerInfo(),
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false, false, 0);
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} else {
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unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
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&SP::IntRegsRegClass);
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LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
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}
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// Compose the two halves together into an i64 unit.
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SDValue WholeValue =
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DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
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// If we want a double, do a bit convert.
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if (ObjectVT == MVT::f64)
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WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
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WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
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InVals.push_back(WholeValue);
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continue;
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}
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ArgOffset += 8;
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break;
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unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
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MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
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SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
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if (VA.getLocVT() == MVT::f32)
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Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
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else if (VA.getLocVT() != MVT::i32) {
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Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
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DAG.getValueType(VA.getLocVT()));
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Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
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}
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InVals.push_back(Arg);
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continue;
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}
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assert(VA.isMemLoc());
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unsigned Offset = VA.getLocMemOffset()+StackOffset;
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if (VA.needsCustom()) {
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assert(VA.getValVT() == MVT::f64);
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//If it is double-word aligned, just load.
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if (Offset % 8 == 0) {
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int FI = MF.getFrameInfo()->CreateFixedObject(8,
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Offset,
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true);
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SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
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SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
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MachinePointerInfo(),
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false,false, 0);
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InVals.push_back(Load);
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continue;
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}
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int FI = MF.getFrameInfo()->CreateFixedObject(4,
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Offset,
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true);
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SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
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SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
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MachinePointerInfo(),
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false, false, 0);
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int FI2 = MF.getFrameInfo()->CreateFixedObject(4,
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Offset+4,
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true);
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SDValue FIPtr2 = DAG.getFrameIndex(FI2, getPointerTy());
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SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2,
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MachinePointerInfo(),
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false, false, 0);
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SDValue WholeValue =
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DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
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WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
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InVals.push_back(WholeValue);
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continue;
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}
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int FI = MF.getFrameInfo()->CreateFixedObject(4,
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Offset,
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true);
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SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
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SDValue Load ;
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if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
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Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
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MachinePointerInfo(),
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false, false, 0);
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} else {
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ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
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// Sparc is big endian, so add an offset based on the ObjectVT.
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unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8);
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FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
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DAG.getConstant(Offset, MVT::i32));
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Load = DAG.getExtLoad(LoadOp, MVT::i32, dl, Chain, FIPtr,
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MachinePointerInfo(),
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VA.getValVT(), false, false,0);
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Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load);
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}
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InVals.push_back(Load);
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}
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// Store remaining ArgRegs to the stack if this is a varargs function.
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if (isVarArg) {
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static const unsigned ArgRegs[] = {
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SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
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};
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unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6);
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const unsigned *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
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unsigned ArgOffset = CCInfo.getNextStackOffset();
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if (NumAllocated == 6)
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ArgOffset += StackOffset;
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else {
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assert(!ArgOffset);
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ArgOffset = 68+4*NumAllocated;
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}
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// Remember the vararg offset for the va_start implementation.
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FuncInfo->setVarArgsFrameOffset(ArgOffset);
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@ -273,41 +301,14 @@ SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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// Sparc target does not yet support tail call optimization.
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isTailCall = false;
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#if 0
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// Analyze operands of the call, assigning locations to each operand.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs);
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CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs,
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*DAG.getContext());
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CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
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// Get the size of the outgoing arguments stack space requirement.
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unsigned ArgsSize = CCInfo.getNextStackOffset();
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// FIXME: We can't use this until f64 is known to take two GPRs.
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#else
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(void)CC_Sparc32;
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// Count the size of the outgoing arguments.
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unsigned ArgsSize = 0;
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for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
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switch (Outs[i].VT.SimpleTy) {
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default: llvm_unreachable("Unknown value type!");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::f32:
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ArgsSize += 4;
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break;
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case MVT::i64:
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case MVT::f64:
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ArgsSize += 8;
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break;
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}
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}
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if (ArgsSize > 4*6)
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ArgsSize -= 4*6; // Space for first 6 arguments is prereserved.
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else
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ArgsSize = 0;
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#endif
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// Keep stack frames 8-byte aligned.
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ArgsSize = (ArgsSize+7) & ~7;
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@ -317,96 +318,52 @@ SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
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SmallVector<SDValue, 8> MemOpChains;
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#if 0
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const unsigned StackOffset = 92;
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// Walk the register/memloc assignments, inserting copies/loads.
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
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i != e;
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++i, ++realArgIdx) {
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CCValAssign &VA = ArgLocs[i];
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SDValue Arg = OutVals[i];
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SDValue Arg = OutVals[realArgIdx];
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// Promote the value if needed.
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switch (VA.getLocInfo()) {
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default: llvm_unreachable("Unknown loc info!");
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case CCValAssign::Full: break;
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case CCValAssign::SExt:
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Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
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Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
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break;
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case CCValAssign::ZExt:
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Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
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Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
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break;
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case CCValAssign::AExt:
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Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
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Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
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break;
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case CCValAssign::BCvt:
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Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
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break;
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}
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// Arguments that can be passed on register must be kept at
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// RegsToPass vector
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if (VA.isRegLoc()) {
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RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
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continue;
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}
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if (VA.needsCustom()) {
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assert(VA.getLocVT() == MVT::f64);
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assert(VA.isMemLoc());
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// Create a store off the stack pointer for this argument.
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SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
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// FIXME: VERIFY THAT 68 IS RIGHT.
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SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+68);
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PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
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MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, MachinePointerInfo(),
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false, false, 0));
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}
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#else
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static const unsigned ArgRegs[] = {
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SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
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};
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unsigned ArgOffset = 68;
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|
||||
for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
|
||||
SDValue Val = OutVals[i];
|
||||
EVT ObjectVT = Outs[i].VT;
|
||||
SDValue ValToStore(0, 0);
|
||||
SDValue ValToStore2(0, 0);
|
||||
unsigned ArgOffset1 = 0, ArgOffset2 = 0;
|
||||
switch (ObjectVT.getSimpleVT().SimpleTy) {
|
||||
default: llvm_unreachable("Unhandled argument type!");
|
||||
case MVT::i32:
|
||||
ArgOffset1 = ArgOffset;
|
||||
ArgOffset += 4;
|
||||
|
||||
if (RegsToPass.size() >= 6) {
|
||||
ValToStore = Val;
|
||||
} else {
|
||||
RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
|
||||
}
|
||||
|
||||
break;
|
||||
case MVT::f32:
|
||||
ArgOffset1 = ArgOffset;
|
||||
ArgOffset += 4;
|
||||
if (RegsToPass.size() >= 6) {
|
||||
ValToStore = Val;
|
||||
} else {
|
||||
// Convert this to a FP value in an int reg.
|
||||
Val = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Val);
|
||||
RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
|
||||
}
|
||||
break;
|
||||
case MVT::f64: {
|
||||
|
||||
if (RegsToPass.size() >= 6) {
|
||||
if (ArgOffset % 8 == 0) {
|
||||
ArgOffset1 = ArgOffset;
|
||||
ArgOffset += 8;
|
||||
ValToStore = Val; // Whole thing is passed in memory.
|
||||
break;
|
||||
if (VA.isMemLoc()) {
|
||||
unsigned Offset = VA.getLocMemOffset() + StackOffset;
|
||||
//if it is double-word aligned, just store.
|
||||
if (Offset % 8 == 0) {
|
||||
SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
|
||||
SDValue PtrOff = DAG.getIntPtrConstant(Offset);
|
||||
PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
|
||||
MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
|
||||
MachinePointerInfo(),
|
||||
false, false, 0));
|
||||
continue;
|
||||
}
|
||||
}
|
||||
// Break into top and bottom parts by storing to the stack and loading
|
||||
// out the parts as integers.
|
||||
|
||||
SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
|
||||
SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
|
||||
Val, StackPtr, MachinePointerInfo(),
|
||||
Arg, StackPtr, MachinePointerInfo(),
|
||||
false, false, 0);
|
||||
// Sparc is big-endian, so the high part comes first.
|
||||
SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
|
||||
|
|
@ -418,74 +375,64 @@ SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||
SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
|
||||
MachinePointerInfo(), false, false, 0);
|
||||
|
||||
if (RegsToPass.size() >= 6) {
|
||||
ArgOffset1 = ArgOffset;
|
||||
ValToStore = Hi;
|
||||
} else {
|
||||
RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
|
||||
}
|
||||
ArgOffset += 4;
|
||||
if (RegsToPass.size() >= 6) {
|
||||
ArgOffset2 = ArgOffset;
|
||||
ValToStore2 = Lo;
|
||||
} else {
|
||||
RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Lo));
|
||||
}
|
||||
ArgOffset += 4;
|
||||
break;
|
||||
}
|
||||
case MVT::i64: {
|
||||
|
||||
if (RegsToPass.size() >= 6) {
|
||||
if (ArgOffset % 8 == 0) {
|
||||
ArgOffset1 = ArgOffset;
|
||||
ArgOffset += 8;
|
||||
ValToStore = Val; // Whole thing is passed in memory.
|
||||
break;
|
||||
if (VA.isRegLoc()) {
|
||||
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi));
|
||||
assert(i+1 != e);
|
||||
CCValAssign &NextVA = ArgLocs[++i];
|
||||
if (NextVA.isRegLoc()) {
|
||||
RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo));
|
||||
} else {
|
||||
//Store the low part in stack.
|
||||
unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
|
||||
SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
|
||||
SDValue PtrOff = DAG.getIntPtrConstant(Offset);
|
||||
PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
|
||||
MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
|
||||
MachinePointerInfo(),
|
||||
false, false, 0));
|
||||
}
|
||||
}
|
||||
|
||||
// Split the value into top and bottom part. Top part goes in a reg.
|
||||
SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val,
|
||||
DAG.getConstant(1, MVT::i32));
|
||||
SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val,
|
||||
DAG.getConstant(0, MVT::i32));
|
||||
if (RegsToPass.size() >= 6) {
|
||||
ArgOffset1 = ArgOffset;
|
||||
ValToStore = Hi;
|
||||
} else {
|
||||
RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
|
||||
unsigned Offset = VA.getLocMemOffset() + StackOffset;
|
||||
// Store the high part.
|
||||
SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
|
||||
SDValue PtrOff = DAG.getIntPtrConstant(Offset);
|
||||
PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
|
||||
MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff,
|
||||
MachinePointerInfo(),
|
||||
false, false, 0));
|
||||
// Store the low part.
|
||||
PtrOff = DAG.getIntPtrConstant(Offset+4);
|
||||
PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
|
||||
MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
|
||||
MachinePointerInfo(),
|
||||
false, false, 0));
|
||||
}
|
||||
ArgOffset += 4;
|
||||
if (RegsToPass.size() >= 6) {
|
||||
ArgOffset2 = ArgOffset;
|
||||
ValToStore2 = Lo;
|
||||
} else {
|
||||
RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Lo));
|
||||
}
|
||||
ArgOffset += 4;
|
||||
break;
|
||||
}
|
||||
continue;
|
||||
}
|
||||
|
||||
if (ValToStore.getNode()) {
|
||||
SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
|
||||
SDValue PtrOff = DAG.getConstant(ArgOffset1, MVT::i32);
|
||||
PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
|
||||
MemOpChains.push_back(DAG.getStore(Chain, dl, ValToStore,
|
||||
PtrOff, MachinePointerInfo(),
|
||||
false, false, 0));
|
||||
}
|
||||
if (ValToStore2.getNode()) {
|
||||
SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
|
||||
SDValue PtrOff = DAG.getConstant(ArgOffset2, MVT::i32);
|
||||
PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
|
||||
MemOpChains.push_back(DAG.getStore(Chain, dl, ValToStore2,
|
||||
PtrOff, MachinePointerInfo(),
|
||||
false, false, 0));
|
||||
// Arguments that can be passed on register must be kept at
|
||||
// RegsToPass vector
|
||||
if (VA.isRegLoc()) {
|
||||
if (VA.getLocVT() != MVT::f32) {
|
||||
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
|
||||
continue;
|
||||
}
|
||||
Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
|
||||
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
|
||||
continue;
|
||||
}
|
||||
|
||||
assert(VA.isMemLoc());
|
||||
|
||||
// Create a store off the stack pointer for this argument.
|
||||
SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
|
||||
SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset);
|
||||
PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
|
||||
MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
|
||||
MachinePointerInfo(),
|
||||
false, false, 0));
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// Emit all stores, make sure the occur before any copies into physregs.
|
||||
if (!MemOpChains.empty())
|
||||
|
|
|
|||
Loading…
Reference in New Issue