forked from OSchip/llvm-project
Revert "Revert "[AArch64][GlobalISel] Optimize G_FCMP + G_SELECT pairs when G_SELECT is fp""
When looking through copies, make sure to not try to find the vreg def of a physreg. Normally getVRegDef will return nullptr in this case, but if there happens to be multiple defs then it will assert. This fixes PR42129. llvm-svn: 362666
This commit is contained in:
Amara Emerson
parent
34c8b835b1
commit
c37ff0d138
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@ -172,6 +172,7 @@ private:
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bool tryOptVectorShuffle(MachineInstr &I) const;
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bool tryOptVectorDup(MachineInstr &MI) const;
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bool tryOptSelect(MachineInstr &MI) const;
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const AArch64TargetMachine &TM;
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const AArch64Subtarget &STI;
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@ -741,6 +742,19 @@ static unsigned selectFPConvOpc(unsigned GenericOpc, LLT DstTy, LLT SrcTy) {
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return GenericOpc;
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}
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static unsigned selectSelectOpc(MachineInstr &I, MachineRegisterInfo &MRI,
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const RegisterBankInfo &RBI) {
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const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
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bool IsFP = (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() !=
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AArch64::GPRRegBankID);
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LLT Ty = MRI.getType(I.getOperand(0).getReg());
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if (Ty == LLT::scalar(32))
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return IsFP ? AArch64::FCSELSrrr : AArch64::CSELWr;
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else if (Ty == LLT::scalar(64) || Ty == LLT::pointer(0, 64))
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return IsFP ? AArch64::FCSELDrrr : AArch64::CSELXr;
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return 0;
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}
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/// Helper function to select the opcode for a G_FCMP.
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static unsigned selectFCMPOpc(MachineInstr &I, MachineRegisterInfo &MRI) {
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// If this is a compare against +0.0, then we don't have to explicitly
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@ -1774,16 +1788,11 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
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// select instead of an integer select.
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bool IsFP = (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() !=
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AArch64::GPRRegBankID);
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unsigned CSelOpc = 0;
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if (Ty == LLT::scalar(32)) {
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CSelOpc = IsFP ? AArch64::FCSELSrrr : AArch64::CSELWr;
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} else if (Ty == LLT::scalar(64) || Ty == LLT::pointer(0, 64)) {
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CSelOpc = IsFP ? AArch64::FCSELDrrr : AArch64::CSELXr;
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} else {
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return false;
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}
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if (IsFP && tryOptSelect(I))
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return true;
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unsigned CSelOpc = selectSelectOpc(I, MRI, RBI);
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MachineInstr &TstMI =
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*BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ANDSWri))
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.addDef(AArch64::WZR)
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@ -2810,6 +2819,85 @@ MachineInstr *AArch64InstructionSelector::emitFMovForFConstant(
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return &I;
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}
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bool AArch64InstructionSelector::tryOptSelect(MachineInstr &I) const {
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MachineIRBuilder MIB(I);
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MachineRegisterInfo &MRI = *MIB.getMRI();
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const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
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// We want to recognize this pattern:
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//
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// $z = G_FCMP pred, $x, $y
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// ...
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// $w = G_SELECT $z, $a, $b
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//
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// Where the value of $z is *only* ever used by the G_SELECT (possibly with
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// some copies/truncs in between.)
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//
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// If we see this, then we can emit something like this:
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//
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// fcmp $x, $y
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// fcsel $w, $a, $b, pred
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//
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// Rather than emitting both of the rather long sequences in the standard
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// G_FCMP/G_SELECT select methods.
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// First, check if the condition is defined by a compare.
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MachineInstr *CondDef = MRI.getVRegDef(I.getOperand(1).getReg());
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while (CondDef) {
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// We can only fold if all of the defs have one use.
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if (!MRI.hasOneUse(CondDef->getOperand(0).getReg()))
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return false;
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// We can skip over G_TRUNC since the condition is 1-bit.
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// Truncating/extending can have no impact on the value.
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unsigned Opc = CondDef->getOpcode();
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if (Opc != TargetOpcode::COPY && Opc != TargetOpcode::G_TRUNC)
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break;
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CondDef = MRI.getVRegDef(CondDef->getOperand(1).getReg());
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}
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// Is the condition defined by a compare?
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// TODO: Handle G_ICMP.
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if (!CondDef || CondDef->getOpcode() != TargetOpcode::G_FCMP)
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return false;
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// Get the condition code for the select.
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AArch64CC::CondCode CondCode;
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AArch64CC::CondCode CondCode2;
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changeFCMPPredToAArch64CC(
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(CmpInst::Predicate)CondDef->getOperand(1).getPredicate(), CondCode,
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CondCode2);
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// changeFCMPPredToAArch64CC sets CondCode2 to AL when we require two
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// instructions to emit the comparison.
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// TODO: Handle FCMP_UEQ and FCMP_ONE. After that, this check will be
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// unnecessary.
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if (CondCode2 != AArch64CC::AL)
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return false;
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// Make sure we'll be able to select the compare.
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unsigned CmpOpc = selectFCMPOpc(*CondDef, MRI);
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if (!CmpOpc)
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return false;
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// Emit a new compare.
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auto Cmp = MIB.buildInstr(CmpOpc, {}, {CondDef->getOperand(2).getReg()});
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if (CmpOpc != AArch64::FCMPSri && CmpOpc != AArch64::FCMPDri)
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Cmp.addUse(CondDef->getOperand(3).getReg());
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// Emit the select.
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unsigned CSelOpc = selectSelectOpc(I, MRI, RBI);
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auto CSel =
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MIB.buildInstr(CSelOpc, {I.getOperand(0).getReg()},
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{I.getOperand(2).getReg(), I.getOperand(3).getReg()})
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.addImm(CondCode);
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constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI);
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constrainSelectedInstRegOperands(*CSel, TII, TRI, RBI);
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I.eraseFromParent();
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return true;
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}
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bool AArch64InstructionSelector::tryOptVectorDup(MachineInstr &I) const {
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// Try to match a vector splat operation into a dup instruction.
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// We're looking for this pattern:
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@ -0,0 +1,351 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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#
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# Verify the following:
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#
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# - We can fold compares into selects.
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# - This only happens when the result of the compare is only used by the select.
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#
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# Also verify that, for now:
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#
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# - We only support doing this with G_FCMP.
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# - We only support condition flags that require a single instruction.
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#
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...
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---
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name: fcmp_more_than_one_user_no_fold
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $s0, $s1, $w1
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; CHECK-LABEL: name: fcmp_more_than_one_user_no_fold
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; CHECK: liveins: $s0, $s1, $w1
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
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; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
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; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[CSINCWr]]
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; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
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; CHECK: $wzr = ANDSWri [[COPY3]], 0, implicit-def $nzcv
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; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 1, implicit $nzcv
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; CHECK: $w1 = COPY [[CSINCWr]]
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; CHECK: $s0 = COPY [[FCSELSrrr]]
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; CHECK: RET_ReallyLR implicit $s0
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%0:fpr(s32) = COPY $s0
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%1:fpr(s32) = COPY $s1
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%2:fpr(s32) = G_FCONSTANT float 0.000000e+00
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%5:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2
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%3:gpr(s1) = G_TRUNC %5(s32)
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%6:fpr(s1) = COPY %3(s1)
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%4:fpr(s32) = G_SELECT %6(s1), %2, %1
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$w1 = COPY %5(s32)
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$s0 = COPY %4(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: using_icmp
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $s0, $w0
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; CHECK-LABEL: name: using_icmp
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; CHECK: liveins: $s0, $w0
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
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; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
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; CHECK: $wzr = SUBSWrr [[COPY]], [[MOVi32imm]], implicit-def $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[CSINCWr]]
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; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
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; CHECK: $wzr = ANDSWri [[COPY3]], 0, implicit-def $nzcv
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; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv
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; CHECK: $s0 = COPY [[FCSELSrrr]]
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; CHECK: RET_ReallyLR implicit $s0
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%0:gpr(s32) = COPY $w0
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%1:fpr(s32) = COPY $s0
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%2:gpr(s32) = G_CONSTANT i32 0
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%5:fpr(s32) = G_FCONSTANT float 0.000000e+00
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%6:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2
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%3:gpr(s1) = G_TRUNC %6(s32)
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%7:fpr(s1) = COPY %3(s1)
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%4:fpr(s32) = G_SELECT %7(s1), %1, %5
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$s0 = COPY %4(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: foeq
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $s0, $s1
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; CHECK-LABEL: name: foeq
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; CHECK: liveins: $s0, $s1
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
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; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
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; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
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; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 0, implicit $nzcv
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; CHECK: $s0 = COPY [[FCSELSrrr]]
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; CHECK: RET_ReallyLR implicit $s0
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%0:fpr(s32) = COPY $s0
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%1:fpr(s32) = COPY $s1
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%2:fpr(s32) = G_FCONSTANT float 0.000000e+00
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%5:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2
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%3:gpr(s1) = G_TRUNC %5(s32)
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%6:fpr(s1) = COPY %3(s1)
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%4:fpr(s32) = G_SELECT %6(s1), %2, %1
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$s0 = COPY %4(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: fueq
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $s0, $s1
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; CHECK-LABEL: name: fueq
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; CHECK: liveins: $s0, $s1
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
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; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
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; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
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; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
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; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]]
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; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
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; CHECK: $wzr = ANDSWri [[COPY3]], 0, implicit-def $nzcv
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; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 1, implicit $nzcv
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; CHECK: $s0 = COPY [[FCSELSrrr]]
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; CHECK: RET_ReallyLR implicit $s0
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%0:fpr(s32) = COPY $s0
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%1:fpr(s32) = COPY $s1
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%2:fpr(s32) = G_FCONSTANT float 0.000000e+00
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%5:gpr(s32) = G_FCMP floatpred(ueq), %0(s32), %2
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%3:gpr(s1) = G_TRUNC %5(s32)
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%6:fpr(s1) = COPY %3(s1)
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%4:fpr(s32) = G_SELECT %6(s1), %2, %1
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$s0 = COPY %4(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: fone
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $s0, $s1
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; CHECK-LABEL: name: fone
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; CHECK: liveins: $s0, $s1
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
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; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
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; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
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; CHECK: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
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; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
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; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]]
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; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
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; CHECK: $wzr = ANDSWri [[COPY3]], 0, implicit-def $nzcv
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; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv
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; CHECK: $s0 = COPY [[FCSELSrrr]]
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; CHECK: RET_ReallyLR implicit $s0
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%0:fpr(s32) = COPY $s0
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%1:fpr(s32) = COPY $s1
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%2:fpr(s32) = G_FCONSTANT float 0.000000e+00
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%5:gpr(s32) = G_FCMP floatpred(one), %0(s32), %2
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%3:gpr(s1) = G_TRUNC %5(s32)
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%6:fpr(s1) = COPY %3(s1)
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%4:fpr(s32) = G_SELECT %6(s1), %1, %2
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$s0 = COPY %4(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: fune
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $s0, $s1
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; CHECK-LABEL: name: fune
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; CHECK: liveins: $s0, $s1
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
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; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
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; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
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; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv
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; CHECK: $s0 = COPY [[FCSELSrrr]]
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; CHECK: RET_ReallyLR implicit $s0
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%0:fpr(s32) = COPY $s0
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%1:fpr(s32) = COPY $s1
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%2:fpr(s32) = G_FCONSTANT float 0.000000e+00
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%5:gpr(s32) = G_FCMP floatpred(une), %0(s32), %2
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%3:gpr(s1) = G_TRUNC %5(s32)
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%6:fpr(s1) = COPY %3(s1)
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%4:fpr(s32) = G_SELECT %6(s1), %1, %2
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$s0 = COPY %4(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: doeq
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $d1
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; CHECK-LABEL: name: doeq
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
|
||||
; CHECK: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
|
||||
; CHECK: FCMPDri [[COPY]], implicit-def $nzcv
|
||||
; CHECK: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[FMOVD0_]], [[COPY1]], 0, implicit $nzcv
|
||||
; CHECK: $d0 = COPY [[FCSELDrrr]]
|
||||
; CHECK: RET_ReallyLR implicit $d0
|
||||
%0:fpr(s64) = COPY $d0
|
||||
%1:fpr(s64) = COPY $d1
|
||||
%2:fpr(s64) = G_FCONSTANT double 0.000000e+00
|
||||
%5:gpr(s32) = G_FCMP floatpred(oeq), %0(s64), %2
|
||||
%3:gpr(s1) = G_TRUNC %5(s32)
|
||||
%6:fpr(s1) = COPY %3(s1)
|
||||
%4:fpr(s64) = G_SELECT %6(s1), %2, %1
|
||||
$d0 = COPY %4(s64)
|
||||
RET_ReallyLR implicit $d0
|
||||
|
||||
...
|
||||
---
|
||||
name: dueq
|
||||
alignment: 2
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $d0, $d1
|
||||
|
||||
; CHECK-LABEL: name: dueq
|
||||
; CHECK: liveins: $d0, $d1
|
||||
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
|
||||
; CHECK: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
|
||||
; CHECK: FCMPDri [[COPY]], implicit-def $nzcv
|
||||
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
|
||||
; CHECK: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
|
||||
; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
|
||||
; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]]
|
||||
; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
|
||||
; CHECK: $wzr = ANDSWri [[COPY3]], 0, implicit-def $nzcv
|
||||
; CHECK: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[FMOVD0_]], [[COPY1]], 1, implicit $nzcv
|
||||
; CHECK: $d0 = COPY [[FCSELDrrr]]
|
||||
; CHECK: RET_ReallyLR implicit $d0
|
||||
%0:fpr(s64) = COPY $d0
|
||||
%1:fpr(s64) = COPY $d1
|
||||
%2:fpr(s64) = G_FCONSTANT double 0.000000e+00
|
||||
%5:gpr(s32) = G_FCMP floatpred(ueq), %0(s64), %2
|
||||
%3:gpr(s1) = G_TRUNC %5(s32)
|
||||
%6:fpr(s1) = COPY %3(s1)
|
||||
%4:fpr(s64) = G_SELECT %6(s1), %2, %1
|
||||
$d0 = COPY %4(s64)
|
||||
RET_ReallyLR implicit $d0
|
||||
|
||||
...
|
||||
---
|
||||
name: done
|
||||
alignment: 2
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $d0, $d1
|
||||
|
||||
; CHECK-LABEL: name: done
|
||||
; CHECK: liveins: $d0, $d1
|
||||
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
|
||||
; CHECK: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
|
||||
; CHECK: FCMPDri [[COPY]], implicit-def $nzcv
|
||||
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
|
||||
; CHECK: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
|
||||
; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
|
||||
; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]]
|
||||
; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
|
||||
; CHECK: $wzr = ANDSWri [[COPY3]], 0, implicit-def $nzcv
|
||||
; CHECK: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[FMOVD0_]], 1, implicit $nzcv
|
||||
; CHECK: $d0 = COPY [[FCSELDrrr]]
|
||||
; CHECK: RET_ReallyLR implicit $d0
|
||||
%0:fpr(s64) = COPY $d0
|
||||
%1:fpr(s64) = COPY $d1
|
||||
%2:fpr(s64) = G_FCONSTANT double 0.000000e+00
|
||||
%5:gpr(s32) = G_FCMP floatpred(one), %0(s64), %2
|
||||
%3:gpr(s1) = G_TRUNC %5(s32)
|
||||
%6:fpr(s1) = COPY %3(s1)
|
||||
%4:fpr(s64) = G_SELECT %6(s1), %1, %2
|
||||
$d0 = COPY %4(s64)
|
||||
RET_ReallyLR implicit $d0
|
||||
|
||||
...
|
||||
---
|
||||
name: dune
|
||||
alignment: 2
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $d0, $d1
|
||||
|
||||
; CHECK-LABEL: name: dune
|
||||
; CHECK: liveins: $d0, $d1
|
||||
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
|
||||
; CHECK: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
|
||||
; CHECK: FCMPDri [[COPY]], implicit-def $nzcv
|
||||
; CHECK: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[FMOVD0_]], 1, implicit $nzcv
|
||||
; CHECK: $d0 = COPY [[FCSELDrrr]]
|
||||
; CHECK: RET_ReallyLR implicit $d0
|
||||
%0:fpr(s64) = COPY $d0
|
||||
%1:fpr(s64) = COPY $d1
|
||||
%2:fpr(s64) = G_FCONSTANT double 0.000000e+00
|
||||
%5:gpr(s32) = G_FCMP floatpred(une), %0(s64), %2
|
||||
%3:gpr(s1) = G_TRUNC %5(s32)
|
||||
%6:fpr(s1) = COPY %3(s1)
|
||||
%4:fpr(s64) = G_SELECT %6(s1), %1, %2
|
||||
$d0 = COPY %4(s64)
|
||||
RET_ReallyLR implicit $d0
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue