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AMDGPU/GlobalISel: Select G_PTR_MASK 

llvm-svn: 371412
This commit is contained in:
Matt Arsenault 2019-09-09 15:46:13 +00:00
parent fdb7030117
commit c34b4036ff
4 changed files with 545 additions and 0 deletions
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65
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
View File

@ -1271,6 +1271,69 @@ bool AMDGPUInstructionSelector::selectG_FRAME_INDEX(MachineInstr &I) const {
DstReg, IsVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass, MRI);
}
bool AMDGPUInstructionSelector::selectG_PTR_MASK(MachineInstr &I) const {
uint64_t Align = I.getOperand(2).getImm();
const uint64_t Mask = ~((UINT64_C(1) << Align) - 1);
MachineBasicBlock *BB = I.getParent();
MachineFunction *MF = BB->getParent();
MachineRegisterInfo &MRI = MF->getRegInfo();
Register DstReg = I.getOperand(0).getReg();
Register SrcReg = I.getOperand(1).getReg();
const RegisterBank *DstRB = RBI.getRegBank(DstReg, MRI, TRI);
const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, MRI, TRI);
const bool IsVGPR = DstRB->getID() == AMDGPU::VGPRRegBankID;
unsigned NewOpc = IsVGPR ? AMDGPU::V_AND_B32_e64 : AMDGPU::S_AND_B32;
unsigned MovOpc = IsVGPR ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32;
const TargetRegisterClass &RegRC
= IsVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass;
LLT Ty = MRI.getType(DstReg);
const TargetRegisterClass *DstRC = TRI.getRegClassForTypeOnBank(Ty, *DstRB,
MRI);
const TargetRegisterClass *SrcRC = TRI.getRegClassForTypeOnBank(Ty, *SrcRB,
MRI);
if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI) ||
!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI))
return false;
const DebugLoc &DL = I.getDebugLoc();
Register ImmReg = MRI.createVirtualRegister(&RegRC);
BuildMI(*BB, &I, DL, TII.get(MovOpc), ImmReg)
.addImm(Mask);
if (Ty.getSizeInBits() == 32) {
BuildMI(*BB, &I, DL, TII.get(NewOpc), DstReg)
.addReg(SrcReg)
.addReg(ImmReg);
I.eraseFromParent();
return true;
}
Register HiReg = MRI.createVirtualRegister(&RegRC);
Register LoReg = MRI.createVirtualRegister(&RegRC);
Register MaskLo = MRI.createVirtualRegister(&RegRC);
BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), LoReg)
.addReg(SrcReg, 0, AMDGPU::sub0);
BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), HiReg)
.addReg(SrcReg, 0, AMDGPU::sub1);
BuildMI(*BB, &I, DL, TII.get(NewOpc), MaskLo)
.addReg(LoReg)
.addReg(ImmReg);
BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
.addReg(MaskLo)
.addImm(AMDGPU::sub0)
.addReg(HiReg)
.addImm(AMDGPU::sub1);
I.eraseFromParent();
return true;
}
bool AMDGPUInstructionSelector::select(MachineInstr &I) {
if (I.isPHI())
return selectPHI(I);
@ -1354,6 +1417,8 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I) {
// is checking for G_CONSTANT
I.setDesc(TII.get(AMDGPU::ATOMIC_FENCE));
return true;
case TargetOpcode::G_PTR_MASK:
return selectG_PTR_MASK(I);
default:
return selectImpl(I, *CoverageInfo);
}

1
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
View File

@ -96,6 +96,7 @@ private:
bool selectG_SELECT(MachineInstr &I) const;
bool selectG_BRCOND(MachineInstr &I) const;
bool selectG_FRAME_INDEX(MachineInstr &I) const;
bool selectG_PTR_MASK(MachineInstr &I) const;
std::pair<Register, unsigned>
selectVOP3ModsImpl(Register Src, const MachineRegisterInfo &MRI) const;

4
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
View File

@ -392,6 +392,10 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.legalForCartesianProduct(AddrSpaces32, {S32})
.scalarize(0);
getActionDefinitionsBuilder(G_PTR_MASK)
.scalarize(0)
.alwaysLegal();
setAction({G_BLOCK_ADDR, CodePtr}, Legal);
auto &CmpBuilder =

475
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-mask.mir Normal file
View File

@ -0,0 +1,475 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
---
name: ptr_mask_p3_sgpr_sgpr_1
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: ptr_mask_p3_sgpr_sgpr_1
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -2
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
%0:sgpr(p3) = COPY $sgpr0
%1:sgpr(p3) = G_PTR_MASK %0, 1
S_ENDPGM 0, implicit %1
...
---
name: ptr_mask_p3_sgpr_sgpr_2
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: ptr_mask_p3_sgpr_sgpr_2
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
%0:sgpr(p3) = COPY $sgpr0
%1:sgpr(p3) = G_PTR_MASK %0, 2
S_ENDPGM 0, implicit %1
...
---
name: ptr_mask_p3_sgpr_sgpr_3
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: ptr_mask_p3_sgpr_sgpr_3
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -8
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
%0:sgpr(p3) = COPY $sgpr0
%1:sgpr(p3) = G_PTR_MASK %0, 3
S_ENDPGM 0, implicit %1
...
---
name: ptr_mask_p3_sgpr_sgpr_4
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: ptr_mask_p3_sgpr_sgpr_4
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -16
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
%0:sgpr(p3) = COPY $sgpr0
%1:sgpr(p3) = G_PTR_MASK %0, 4
S_ENDPGM 0, implicit %1
...
---
name: ptr_mask_p3_sgpr_sgpr_29
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: ptr_mask_p3_sgpr_sgpr_29
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -16
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
%0:sgpr(p3) = COPY $sgpr0
%1:sgpr(p3) = G_PTR_MASK %0, 4
S_ENDPGM 0, implicit %1
...
---
name: ptr_mask_p0_sgpr_sgpr_1
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: ptr_mask_p0_sgpr_sgpr_1
; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(p0) = COPY $sgpr0_sgpr1
%1:sgpr(p0) = G_PTR_MASK %0, 1
S_ENDPGM 0, implicit %1
...
---
name: ptr_mask_p0_sgpr_sgpr_2
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: ptr_mask_p0_sgpr_sgpr_2
; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4
; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(p0) = COPY $sgpr0_sgpr1
%1:sgpr(p0) = G_PTR_MASK %0, 2
S_ENDPGM 0, implicit %1
...
---
name: ptr_mask_p0_sgpr_sgpr_3
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: ptr_mask_p0_sgpr_sgpr_3
; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -8
; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(p0) = COPY $sgpr0_sgpr1
%1:sgpr(p0) = G_PTR_MASK %0, 3
S_ENDPGM 0, implicit %1
...
---
name: ptr_mask_p0_sgpr_sgpr_4
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: ptr_mask_p0_sgpr_sgpr_4
; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -16
; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(p0) = COPY $sgpr0_sgpr1
%1:sgpr(p0) = G_PTR_MASK %0, 4
S_ENDPGM 0, implicit %1
...
---
name: ptr_mask_p0_sgpr_sgpr_29
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: ptr_mask_p0_sgpr_sgpr_29
; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -16
; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(p0) = COPY $sgpr0_sgpr1
%1:sgpr(p0) = G_PTR_MASK %0, 4
S_ENDPGM 0, implicit %1
...
---
name: ptr_mask_p3_vgpr_vgpr_1
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: ptr_mask_p3_vgpr_vgpr_1
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -2, implicit $exec
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
%0:vgpr(p3) = COPY $vgpr0
%1:vgpr(p3) = G_PTR_MASK %0, 1
S_ENDPGM 0, implicit %1
...
---
name: ptr_mask_p3_vgpr_vgpr_2
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: ptr_mask_p3_vgpr_vgpr_2
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
%0:vgpr(p3) = COPY $vgpr0
%1:vgpr(p3) = G_PTR_MASK %0, 2
S_ENDPGM 0, implicit %1
...
---
name: ptr_mask_p3_vgpr_vgpr_3
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: ptr_mask_p3_vgpr_vgpr_3
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
%0:vgpr(p3) = COPY $vgpr0
%1:vgpr(p3) = G_PTR_MASK %0, 2
S_ENDPGM 0, implicit %1
...
---
name: ptr_mask_p3_vgpr_vgpr_4
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: ptr_mask_p3_vgpr_vgpr_4
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -16, implicit $exec
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
%0:vgpr(p3) = COPY $vgpr0
%1:vgpr(p3) = G_PTR_MASK %0, 4
S_ENDPGM 0, implicit %1
...
---
name: ptr_mask_p3_vgpr_vgpr_29
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: ptr_mask_p3_vgpr_vgpr_29
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -16, implicit $exec
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
%0:vgpr(p3) = COPY $vgpr0
%1:vgpr(p3) = G_PTR_MASK %0, 4
S_ENDPGM 0, implicit %1
...
---
name: ptr_mask_p0_vgpr_vgpr_1
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: ptr_mask_p0_vgpr_vgpr_1
; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -2, implicit $exec
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:vgpr(p0) = COPY $vgpr0_vgpr1
%1:vgpr(p0) = G_PTR_MASK %0, 1
S_ENDPGM 0, implicit %1
...
---
name: ptr_mask_p0_vgpr_vgpr_2
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: ptr_mask_p0_vgpr_vgpr_2
; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:vgpr(p0) = COPY $vgpr0_vgpr1
%1:vgpr(p0) = G_PTR_MASK %0, 2
S_ENDPGM 0, implicit %1
...
---
name: ptr_mask_p0_vgpr_vgpr_3
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: ptr_mask_p0_vgpr_vgpr_3
; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:vgpr(p0) = COPY $vgpr0_vgpr1
%1:vgpr(p0) = G_PTR_MASK %0, 2
S_ENDPGM 0, implicit %1
...
---
name: ptr_mask_p0_vgpr_vgpr_4
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: ptr_mask_p0_vgpr_vgpr_4
; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -16, implicit $exec
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:vgpr(p0) = COPY $vgpr0_vgpr1
%1:vgpr(p0) = G_PTR_MASK %0, 4
S_ENDPGM 0, implicit %1
...
---
name: ptr_mask_p0_vgpr_vgpr_29
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: ptr_mask_p0_vgpr_vgpr_29
; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -16, implicit $exec
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:vgpr(p0) = COPY $vgpr0_vgpr1
%1:vgpr(p0) = G_PTR_MASK %0, 4
S_ENDPGM 0, implicit %1
...
---
name: ptr_mask_p3_vgpr_sgpr_2
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: ptr_mask_p3_vgpr_sgpr_2
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
%0:sgpr(p3) = COPY $sgpr0
%1:vgpr(p3) = G_PTR_MASK %0, 2
S_ENDPGM 0, implicit %1
...
---
name: ptr_mask_p0_vgpr_sgpr_2
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: ptr_mask_p0_vgpr_sgpr_2
; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(p0) = COPY $sgpr0_sgpr1
%1:vgpr(p0) = G_PTR_MASK %0, 2
S_ENDPGM 0, implicit %1
...