forked from OSchip/llvm-project
[UBSan] Adding support of MIPS32
Changed files: config-ix.cmake: Enabled UBSan for MIPS32 sanitizer_stacktrace.cc: Program counter for MIPS32 is four byte aligned and a delay slot so subtracted PC by 8 for getting call site address. cast-overflow.cpp: Added big endian support for this test case. Patch by Sagar Thakur. Differential Revision: http://reviews.llvm.org/D4881 llvm-svn: 218519
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@ -134,7 +134,7 @@ filter_available_targets(LSAN_COMMON_SUPPORTED_ARCH
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filter_available_targets(MSAN_SUPPORTED_ARCH x86_64)
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filter_available_targets(PROFILE_SUPPORTED_ARCH x86_64 i386 arm aarch64)
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filter_available_targets(TSAN_SUPPORTED_ARCH x86_64)
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filter_available_targets(UBSAN_SUPPORTED_ARCH x86_64 i386 arm aarch64)
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filter_available_targets(UBSAN_SUPPORTED_ARCH x86_64 i386 arm aarch64 mips)
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if(ANDROID)
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set(OS_NAME "Android")
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@ -25,7 +25,7 @@ uptr StackTrace::GetPreviousInstructionPc(uptr pc) {
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#if defined(__powerpc__) || defined(__powerpc64__)
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// PCs are always 4 byte aligned.
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return pc - 4;
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#elif defined(__sparc__)
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#elif defined(__sparc__) || defined(__mips__)
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return pc - 8;
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#else
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return pc - 1;
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@ -14,6 +14,7 @@
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// This test assumes float and double are IEEE-754 single- and double-precision.
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#include <endian.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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@ -41,12 +42,20 @@ int main(int argc, char **argv) {
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unsigned Zero = NearlyMinusOne; // ok
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// Build a '+Inf'.
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#if __BYTE_ORDER == __LITTLE_ENDIAN
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char InfVal[] = { 0x00, 0x00, 0x80, 0x7f };
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#else
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char InfVal[] = { 0x7f, 0x80, 0x00, 0x00 };
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#endif
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float Inf;
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memcpy(&Inf, InfVal, 4);
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// Build a 'NaN'.
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#if __BYTE_ORDER == __LITTLE_ENDIAN
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char NaNVal[] = { 0x01, 0x00, 0x80, 0x7f };
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#else
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char NaNVal[] = { 0x7f, 0x80, 0x00, 0x01 };
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#endif
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float NaN;
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memcpy(&NaN, NaNVal, 4);
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