forked from OSchip/llvm-project
[Sparc] Add the initial implementation of an asm parser for sparc/sparcv9.
llvm-svn: 198484
This commit is contained in:
Venkatraman Govindaraju
parent
acb42aefd7
commit
c2dee7dc74
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@ -0,0 +1,3 @@
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add_llvm_library(LLVMSparcAsmParser
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SparcAsmParser.cpp
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)
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;===- ./lib/Target/Sparc/AsmParser/LLVMBuild.txt ---------------*- Conf -*--===;
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;
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; The LLVM Compiler Infrastructure
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;
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; This file is distributed under the University of Illinois Open Source
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; License. See LICENSE.TXT for details.
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;
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;===------------------------------------------------------------------------===;
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;
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; This is an LLVMBuild description file for the components in this subdirectory.
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;
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; For more information on the LLVMBuild system, please see:
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;
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; http://llvm.org/docs/LLVMBuild.html
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;
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;===------------------------------------------------------------------------===;
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[component_0]
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type = Library
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name = SparcAsmParser
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parent = Sparc
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required_libraries = MC MCParser Support SparcDesc SparcInfo
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add_to_library_groups = Sparc
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@ -0,0 +1,15 @@
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##===- lib/Target/Sparc/AsmParser/Makefile ------------------*- Makefile-*-===##
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#
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# The LLVM Compiler Infrastructure
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#
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# This file is distributed under the University of Illinois Open Source
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# License. See LICENSE.TXT for details.
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#
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##===----------------------------------------------------------------------===##
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LEVEL = ../../../..
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LIBRARYNAME = LLVMSparcAsmParser
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# Hack: we need to include 'main' Sparc target directory to grab private headers
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CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
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include $(LEVEL)/Makefile.common
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@ -0,0 +1,614 @@
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//===-- SparcAsmParser.cpp - Parse Sparc assembly to MCInst instructions --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/SparcMCTargetDesc.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCTargetAsmParser.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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// The generated AsmMatcher SparcGenAsmMatcher uses "Sparc" as the target
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// namespace. But SPARC backend uses "SP" as its namespace.
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namespace llvm {
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namespace Sparc {
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using namespace SP;
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}
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}
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namespace {
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class SparcAsmParser : public MCTargetAsmParser {
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MCSubtargetInfo &STI;
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MCAsmParser &Parser;
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/// @name Auto-generated Match Functions
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/// {
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#define GET_ASSEMBLER_HEADER
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#include "SparcGenAsmMatcher.inc"
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/// }
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// public interface of the MCTargetAsmParser.
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bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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MCStreamer &Out, unsigned &ErrorInfo,
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bool MatchingInlineAsm);
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bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
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bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
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SMLoc NameLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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bool ParseDirective(AsmToken DirectiveID);
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// Custom parse functions for Sparc specific operands.
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OperandMatchResultTy
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parseMEMrrOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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OperandMatchResultTy
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parseMEMriOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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OperandMatchResultTy
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parseMEMOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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int ImmOffsetOrReg);
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OperandMatchResultTy
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parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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StringRef Name);
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// returns true if Tok is matched to a register and returns register in RegNo.
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bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo, bool isDFP,
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bool isQFP);
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public:
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SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
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const MCInstrInfo &MII)
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: MCTargetAsmParser(), STI(sti), Parser(parser) {
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// Initialize the set of available features.
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setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
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}
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};
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static unsigned IntRegs[32] = {
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Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3,
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Sparc::G4, Sparc::G5, Sparc::G6, Sparc::G7,
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Sparc::O0, Sparc::O1, Sparc::O2, Sparc::O3,
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Sparc::O4, Sparc::O5, Sparc::O6, Sparc::O7,
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Sparc::L0, Sparc::L1, Sparc::L2, Sparc::L3,
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Sparc::L4, Sparc::L5, Sparc::L6, Sparc::L7,
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Sparc::I0, Sparc::I1, Sparc::I2, Sparc::I3,
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Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };
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static unsigned FloatRegs[32] = {
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Sparc::F0, Sparc::F1, Sparc::F2, Sparc::F3,
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Sparc::F4, Sparc::F5, Sparc::F6, Sparc::F7,
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Sparc::F8, Sparc::F9, Sparc::F10, Sparc::F11,
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Sparc::F12, Sparc::F13, Sparc::F14, Sparc::F15,
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Sparc::F16, Sparc::F17, Sparc::F18, Sparc::F19,
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Sparc::F20, Sparc::F21, Sparc::F22, Sparc::F23,
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Sparc::F24, Sparc::F25, Sparc::F26, Sparc::F27,
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Sparc::F28, Sparc::F29, Sparc::F30, Sparc::F31 };
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static unsigned DoubleRegs[32] = {
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Sparc::D0, Sparc::D1, Sparc::D2, Sparc::D3,
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Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7,
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Sparc::D8, Sparc::D7, Sparc::D8, Sparc::D9,
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Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
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Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19,
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Sparc::D20, Sparc::D21, Sparc::D22, Sparc::D23,
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Sparc::D24, Sparc::D25, Sparc::D26, Sparc::D27,
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Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 };
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static unsigned QuadFPRegs[32] = {
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Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3,
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Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
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Sparc::Q8, Sparc::Q7, Sparc::Q8, Sparc::Q9,
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Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
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/// SparcOperand - Instances of this class represent a parsed Sparc machine
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/// instruction.
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class SparcOperand : public MCParsedAsmOperand {
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public:
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enum RegisterKind {
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rk_None,
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rk_IntReg,
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rk_FloatReg,
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rk_DoubleReg,
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rk_QuadReg,
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rk_CCReg,
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rk_Y
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};
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private:
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enum KindTy {
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k_Token,
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k_Register,
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k_Immediate,
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k_MemoryReg,
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k_MemoryImm
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} Kind;
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SMLoc StartLoc, EndLoc;
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SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
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struct Token {
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const char *Data;
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unsigned Length;
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};
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struct RegOp {
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unsigned RegNum;
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RegisterKind Kind;
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};
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struct ImmOp {
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const MCExpr *Val;
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};
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struct MemOp {
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unsigned Base;
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unsigned OffsetReg;
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const MCExpr *Off;
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};
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union {
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struct Token Tok;
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struct RegOp Reg;
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struct ImmOp Imm;
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struct MemOp Mem;
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};
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public:
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bool isToken() const { return Kind == k_Token; }
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bool isReg() const { return Kind == k_Register; }
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bool isImm() const { return Kind == k_Immediate; }
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bool isMem() const { return isMEMrr() || isMEMri(); }
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bool isMEMrr() const { return Kind == k_MemoryReg; }
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bool isMEMri() const { return Kind == k_MemoryImm; }
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StringRef getToken() const {
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assert(Kind == k_Token && "Invalid access!");
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return StringRef(Tok.Data, Tok.Length);
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}
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unsigned getReg() const {
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assert((Kind == k_Register) && "Invalid access!");
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return Reg.RegNum;
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}
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const MCExpr *getImm() const {
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assert((Kind == k_Immediate) && "Invalid access!");
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return Imm.Val;
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}
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unsigned getMemBase() const {
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assert((Kind == k_MemoryReg || Kind == k_MemoryImm) && "Invalid access!");
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return Mem.Base;
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}
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unsigned getMemOffsetReg() const {
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assert((Kind == k_MemoryReg) && "Invalid access!");
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return Mem.OffsetReg;
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}
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const MCExpr *getMemOff() const {
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assert((Kind == k_MemoryImm) && "Invalid access!");
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return Mem.Off;
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}
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/// getStartLoc - Get the location of the first token of this operand.
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SMLoc getStartLoc() const {
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return StartLoc;
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}
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/// getEndLoc - Get the location of the last token of this operand.
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SMLoc getEndLoc() const {
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return EndLoc;
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}
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virtual void print(raw_ostream &OS) const {
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switch (Kind) {
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case k_Token: OS << "Token: " << getToken() << "\n"; break;
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case k_Register: OS << "Reg: #" << getReg() << "\n"; break;
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case k_Immediate: OS << "Imm: " << getImm() << "\n"; break;
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case k_MemoryReg: OS << "Mem: " << getMemBase() << "+"
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<< getMemOffsetReg() << "\n"; break;
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case k_MemoryImm: assert(getMemOff() != 0);
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OS << "Mem: " << getMemBase()
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<< "+" << *getMemOff()
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<< "\n"; break;
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}
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}
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void addRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(getReg()));
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}
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void addImmOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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const MCExpr *Expr = getImm();
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addExpr(Inst, Expr);
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}
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void addExpr(MCInst &Inst, const MCExpr *Expr) const{
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// Add as immediate when possible. Null MCExpr = 0.
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if (Expr == 0)
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Inst.addOperand(MCOperand::CreateImm(0));
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else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
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Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
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else
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Inst.addOperand(MCOperand::CreateExpr(Expr));
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}
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void addMEMrrOperands(MCInst &Inst, unsigned N) const {
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assert(N == 2 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(getMemBase()));
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assert(getMemOffsetReg() != 0 && "Invalid offset");
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Inst.addOperand(MCOperand::CreateReg(getMemOffsetReg()));
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}
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void addMEMriOperands(MCInst &Inst, unsigned N) const {
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assert(N == 2 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(getMemBase()));
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const MCExpr *Expr = getMemOff();
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addExpr(Inst, Expr);
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}
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static SparcOperand *CreateToken(StringRef Str, SMLoc S) {
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SparcOperand *Op = new SparcOperand(k_Token);
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Op->Tok.Data = Str.data();
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Op->Tok.Length = Str.size();
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Op->StartLoc = S;
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Op->EndLoc = S;
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return Op;
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}
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static SparcOperand *CreateReg(unsigned RegNum,
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SparcOperand::RegisterKind Kind,
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SMLoc S, SMLoc E) {
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SparcOperand *Op = new SparcOperand(k_Register);
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Op->Reg.RegNum = RegNum;
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Op->Reg.Kind = Kind;
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Op->StartLoc = S;
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Op->EndLoc = E;
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return Op;
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}
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static SparcOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
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SparcOperand *Op = new SparcOperand(k_Immediate);
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Op->Imm.Val = Val;
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Op->StartLoc = S;
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Op->EndLoc = E;
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return Op;
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}
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};
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} // end namespace
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bool SparcAsmParser::
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MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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MCStreamer &Out, unsigned &ErrorInfo,
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bool MatchingInlineAsm) {
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MCInst Inst;
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SmallVector<MCInst, 8> Instructions;
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unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
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MatchingInlineAsm);
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switch (MatchResult) {
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default:
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break;
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case Match_Success: {
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Inst.setLoc(IDLoc);
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Out.EmitInstruction(Inst);
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return false;
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}
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case Match_MissingFeature:
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return Error(IDLoc,
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"instruction requires a CPU feature not currently enabled");
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case Match_InvalidOperand: {
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SMLoc ErrorLoc = IDLoc;
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if (ErrorInfo != ~0U) {
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if (ErrorInfo >= Operands.size())
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return Error(IDLoc, "too few operands for instruction");
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ErrorLoc = ((SparcOperand*) Operands[ErrorInfo])->getStartLoc();
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if (ErrorLoc == SMLoc())
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ErrorLoc = IDLoc;
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}
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return Error(ErrorLoc, "invalid operand for instruction");
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}
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case Match_MnemonicFail:
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return Error(IDLoc, "invalid instruction");
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}
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return true;
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}
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bool SparcAsmParser::
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ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc)
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{
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const AsmToken &Tok = Parser.getTok();
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StartLoc = Tok.getLoc();
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EndLoc = Tok.getEndLoc();
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RegNo = 0;
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if (getLexer().getKind() != AsmToken::Percent)
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return false;
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Parser.Lex();
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if (matchRegisterName(Tok, RegNo, false, false)) {
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Parser.Lex();
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return false;
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}
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return Error(StartLoc, "invalid register name");
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}
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bool SparcAsmParser::
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ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
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SMLoc NameLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands)
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{
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// Check if we have valid mnemonic.
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if (!mnemonicIsValid(Name, 0)) {
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Parser.eatToEndOfStatement();
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return Error(NameLoc, "Unknown instruction");
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}
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// First operand in MCInst is instruction mnemonic.
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Operands.push_back(SparcOperand::CreateToken(Name, NameLoc));
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if (getLexer().isNot(AsmToken::EndOfStatement)) {
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// Read the first operand.
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if (parseOperand(Operands, Name) != MatchOperand_Success) {
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SMLoc Loc = getLexer().getLoc();
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Parser.eatToEndOfStatement();
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return Error(Loc, "unexpected token");
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}
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while (getLexer().is(AsmToken::Comma)) {
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Parser.Lex(); // Eat the comma.
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// Parse and remember the operand.
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if (parseOperand(Operands, Name) != MatchOperand_Success) {
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SMLoc Loc = getLexer().getLoc();
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Parser.eatToEndOfStatement();
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return Error(Loc, "unexpected token");
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}
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}
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}
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if (getLexer().isNot(AsmToken::EndOfStatement)) {
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SMLoc Loc = getLexer().getLoc();
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Parser.eatToEndOfStatement();
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return Error(Loc, "unexpected token");
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}
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Parser.Lex(); // Consume the EndOfStatement.
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return false;
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}
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bool SparcAsmParser::
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ParseDirective(AsmToken DirectiveID)
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{
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// Ignore all directives for now.
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Parser.eatToEndOfStatement();
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return false;
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}
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SparcAsmParser::OperandMatchResultTy SparcAsmParser::
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parseMEMOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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int ImmOffsetOrReg)
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{
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// FIXME: Implement memory operand parsing here.
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return MatchOperand_NoMatch;
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}
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SparcAsmParser::OperandMatchResultTy SparcAsmParser::
|
||||
parseMEMrrOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands)
|
||||
{
|
||||
return parseMEMOperand(Operands, 2);
|
||||
}
|
||||
|
||||
SparcAsmParser::OperandMatchResultTy SparcAsmParser::
|
||||
parseMEMriOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands)
|
||||
{
|
||||
return parseMEMOperand(Operands, 1);
|
||||
}
|
||||
|
||||
SparcAsmParser::OperandMatchResultTy SparcAsmParser::
|
||||
parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
|
||||
StringRef Mnemonic)
|
||||
{
|
||||
OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
|
||||
if (ResTy == MatchOperand_Success)
|
||||
return ResTy;
|
||||
// If there wasn't a custom match, try the generic matcher below. Otherwise,
|
||||
// there was a match, but an error occurred, in which case, just return that
|
||||
// the operand parsing failed.
|
||||
if (ResTy == MatchOperand_ParseFail)
|
||||
return ResTy;
|
||||
|
||||
SMLoc S = Parser.getTok().getLoc();
|
||||
SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
|
||||
const MCExpr *EVal;
|
||||
SparcOperand *Op;
|
||||
switch (getLexer().getKind()) {
|
||||
case AsmToken::Percent:
|
||||
Parser.Lex(); // Eat the '%'.
|
||||
unsigned RegNo;
|
||||
if (matchRegisterName(Parser.getTok(), RegNo, false, false)) {
|
||||
Parser.Lex(); // Eat the identifier token.
|
||||
Op = SparcOperand::CreateReg(RegNo, SparcOperand::rk_None, S, E);
|
||||
break;
|
||||
}
|
||||
// FIXME: Handle modifiers like %hi, %lo etc.,
|
||||
return MatchOperand_ParseFail;
|
||||
|
||||
case AsmToken::Minus:
|
||||
case AsmToken::Integer:
|
||||
if (getParser().parseExpression(EVal))
|
||||
return MatchOperand_ParseFail;
|
||||
|
||||
Op = SparcOperand::CreateImm(EVal, S, E);
|
||||
break;
|
||||
|
||||
case AsmToken::Identifier: {
|
||||
StringRef Identifier;
|
||||
if (getParser().parseIdentifier(Identifier))
|
||||
return MatchOperand_ParseFail;
|
||||
SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
|
||||
MCSymbol *Sym = getContext().GetOrCreateSymbol(Identifier);
|
||||
|
||||
// Otherwise create a symbol reference.
|
||||
const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
|
||||
getContext());
|
||||
|
||||
Op = SparcOperand::CreateImm(Res, S, E);
|
||||
break;
|
||||
}
|
||||
|
||||
case AsmToken::LBrac: // handle [
|
||||
return parseMEMOperand(Operands, 0);
|
||||
|
||||
default:
|
||||
return MatchOperand_ParseFail;
|
||||
}
|
||||
// Push the parsed operand into the list of operands
|
||||
Operands.push_back(Op);
|
||||
return MatchOperand_Success;
|
||||
}
|
||||
|
||||
bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
|
||||
unsigned &RegNo,
|
||||
bool isDFP,
|
||||
bool isQFP)
|
||||
{
|
||||
int64_t intVal = 0;
|
||||
RegNo = 0;
|
||||
if (Tok.is(AsmToken::Identifier)) {
|
||||
StringRef name = Tok.getString();
|
||||
|
||||
// %fp
|
||||
if (name.equals("fp")) {
|
||||
RegNo = Sparc::I6;
|
||||
return true;
|
||||
}
|
||||
// %sp
|
||||
if (name.equals("sp")) {
|
||||
RegNo = Sparc::O6;
|
||||
return true;
|
||||
}
|
||||
|
||||
if (name.equals("y")) {
|
||||
RegNo = Sparc::Y;
|
||||
return true;
|
||||
}
|
||||
|
||||
if (name.equals("icc")) {
|
||||
RegNo = Sparc::ICC;
|
||||
return true;
|
||||
}
|
||||
|
||||
if (name.equals("xcc")) {
|
||||
// FIXME:: check 64bit.
|
||||
RegNo = Sparc::ICC;
|
||||
return true;
|
||||
}
|
||||
|
||||
// %fcc0 - %fcc3
|
||||
if (name.substr(0, 3).equals_lower("fcc")
|
||||
&& !name.substr(3).getAsInteger(10, intVal)
|
||||
&& intVal < 4) {
|
||||
// FIXME: check 64bit and handle %fcc1 - %fcc3
|
||||
RegNo = Sparc::FCC;
|
||||
return true;
|
||||
}
|
||||
|
||||
// %g0 - %g7
|
||||
if (name.substr(0, 1).equals_lower("g")
|
||||
&& !name.substr(1).getAsInteger(10, intVal)
|
||||
&& intVal < 8) {
|
||||
RegNo = IntRegs[intVal];
|
||||
return true;
|
||||
}
|
||||
// %o0 - %o7
|
||||
if (name.substr(0, 1).equals_lower("o")
|
||||
&& !name.substr(1).getAsInteger(10, intVal)
|
||||
&& intVal < 8) {
|
||||
RegNo = IntRegs[8 + intVal];
|
||||
return true;
|
||||
}
|
||||
if (name.substr(0, 1).equals_lower("l")
|
||||
&& !name.substr(1).getAsInteger(10, intVal)
|
||||
&& intVal < 8) {
|
||||
RegNo = IntRegs[16 + intVal];
|
||||
return true;
|
||||
}
|
||||
if (name.substr(0, 1).equals_lower("i")
|
||||
&& !name.substr(1).getAsInteger(10, intVal)
|
||||
&& intVal < 8) {
|
||||
RegNo = IntRegs[24 + intVal];
|
||||
return true;
|
||||
}
|
||||
// %f0 - %f31
|
||||
if (name.substr(0, 1).equals_lower("f")
|
||||
&& !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 32) {
|
||||
if (isDFP && (intVal%2 == 0)) {
|
||||
RegNo = DoubleRegs[intVal/2];
|
||||
} else if (isQFP && (intVal%4 == 0)) {
|
||||
RegNo = QuadFPRegs[intVal/4];
|
||||
} else {
|
||||
RegNo = FloatRegs[intVal];
|
||||
}
|
||||
return true;
|
||||
}
|
||||
// %f32 - %f62
|
||||
if (name.substr(0, 1).equals_lower("f")
|
||||
&& !name.substr(1, 2).getAsInteger(10, intVal)
|
||||
&& intVal >= 32 && intVal <= 62 && (intVal % 2 == 0)) {
|
||||
if (isDFP) {
|
||||
RegNo = DoubleRegs[16 + intVal/2];
|
||||
} else if (isQFP && (intVal % 4 == 0)) {
|
||||
RegNo = QuadFPRegs[8 + intVal/4];
|
||||
} else {
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
// %r0 - %r31
|
||||
if (name.substr(0, 1).equals_lower("r")
|
||||
&& !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 31) {
|
||||
RegNo = IntRegs[intVal];
|
||||
return true;
|
||||
}
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
|
||||
extern "C" void LLVMInitializeSparcAsmParser() {
|
||||
RegisterMCAsmParser<SparcAsmParser> A(TheSparcTarget);
|
||||
RegisterMCAsmParser<SparcAsmParser> B(TheSparcV9Target);
|
||||
}
|
||||
|
||||
#define GET_REGISTER_MATCHER
|
||||
#define GET_MATCHER_IMPLEMENTATION
|
||||
#include "SparcGenAsmMatcher.inc"
|
||||
|
|
@ -4,6 +4,7 @@ tablegen(LLVM SparcGenRegisterInfo.inc -gen-register-info)
|
|||
tablegen(LLVM SparcGenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(LLVM SparcGenCodeEmitter.inc -gen-emitter)
|
||||
tablegen(LLVM SparcGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(LLVM SparcGenAsmMatcher.inc -gen-asm-matcher)
|
||||
tablegen(LLVM SparcGenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(LLVM SparcGenSubtargetInfo.inc -gen-subtarget)
|
||||
tablegen(LLVM SparcGenCallingConv.inc -gen-callingconv)
|
||||
|
|
@ -29,3 +30,4 @@ add_llvm_target(SparcCodeGen
|
|||
add_subdirectory(TargetInfo)
|
||||
add_subdirectory(MCTargetDesc)
|
||||
add_subdirectory(InstPrinter)
|
||||
add_subdirectory(AsmParser)
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
;===------------------------------------------------------------------------===;
|
||||
|
||||
[common]
|
||||
subdirectories = InstPrinter MCTargetDesc TargetInfo
|
||||
subdirectories = AsmParser InstPrinter MCTargetDesc TargetInfo
|
||||
|
||||
[component_0]
|
||||
type = TargetGroup
|
||||
|
|
|
|||
|
|
@ -123,13 +123,18 @@ extern "C" void LLVMInitializeSparcTargetMC() {
|
|||
|
||||
// Register the MC instruction info.
|
||||
TargetRegistry::RegisterMCInstrInfo(TheSparcTarget, createSparcMCInstrInfo);
|
||||
TargetRegistry::RegisterMCInstrInfo(TheSparcV9Target, createSparcMCInstrInfo);
|
||||
|
||||
// Register the MC register info.
|
||||
TargetRegistry::RegisterMCRegInfo(TheSparcTarget, createSparcMCRegisterInfo);
|
||||
TargetRegistry::RegisterMCRegInfo(TheSparcV9Target,
|
||||
createSparcMCRegisterInfo);
|
||||
|
||||
// Register the MC subtarget info.
|
||||
TargetRegistry::RegisterMCSubtargetInfo(TheSparcTarget,
|
||||
createSparcMCSubtargetInfo);
|
||||
TargetRegistry::RegisterMCSubtargetInfo(TheSparcV9Target,
|
||||
createSparcMCSubtargetInfo);
|
||||
|
||||
TargetRegistry::RegisterAsmStreamer(TheSparcTarget,
|
||||
createMCAsmStreamer);
|
||||
|
|
|
|||
|
|
@ -13,11 +13,12 @@ TARGET = Sparc
|
|||
|
||||
# Make sure that tblgen is run, first thing.
|
||||
BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrInfo.inc \
|
||||
SparcGenAsmWriter.inc SparcGenDAGISel.inc \
|
||||
SparcGenAsmWriter.inc SparcGenAsmMatcher.inc \
|
||||
SparcGenDAGISel.inc \
|
||||
SparcGenSubtargetInfo.inc SparcGenCallingConv.inc \
|
||||
SparcGenCodeEmitter.inc
|
||||
|
||||
DIRS = InstPrinter TargetInfo MCTargetDesc
|
||||
DIRS = InstPrinter AsmParser TargetInfo MCTargetDesc
|
||||
|
||||
include $(LEVEL)/Makefile.common
|
||||
|
||||
|
|
|
|||
|
|
@ -44,6 +44,10 @@ include "SparcInstrInfo.td"
|
|||
|
||||
def SparcInstrInfo : InstrInfo;
|
||||
|
||||
def SparcAsmParser : AsmParser {
|
||||
bit ShouldEmitMatchRegisterName = 0;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// SPARC processors supported.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
@ -73,4 +77,5 @@ def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
|
|||
def Sparc : Target {
|
||||
// Pull in Instruction Info:
|
||||
let InstructionSet = SparcInstrInfo;
|
||||
let AssemblyParsers = [SparcAsmParser];
|
||||
}
|
||||
|
|
|
|||
|
|
@ -176,11 +176,11 @@ def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>;
|
|||
def : Pat<(ctpop i64:$src), (POPCrr $src)>;
|
||||
|
||||
// "LEA" form of add
|
||||
let isCodeGenOnly = 1 in
|
||||
def LEAX_ADDri : F3_2<2, 0b000000,
|
||||
(outs I64Regs:$dst), (ins MEMri:$addr),
|
||||
"add ${addr:arith}, $dst",
|
||||
[(set iPTR:$dst, ADDRri:$addr)]>;
|
||||
|
||||
} // Predicates = [Is64Bit]
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -76,13 +76,25 @@ def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
|
|||
def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
|
||||
|
||||
// Address operands
|
||||
def SparcMEMrrAsmOperand : AsmOperandClass {
|
||||
let Name = "MEMrr";
|
||||
let ParserMethod = "parseMEMrrOperand";
|
||||
}
|
||||
|
||||
def SparcMEMriAsmOperand : AsmOperandClass {
|
||||
let Name = "MEMri";
|
||||
let ParserMethod = "parseMEMriOperand";
|
||||
}
|
||||
|
||||
def MEMrr : Operand<iPTR> {
|
||||
let PrintMethod = "printMemOperand";
|
||||
let MIOperandInfo = (ops ptr_rc, ptr_rc);
|
||||
let ParserMatchClass = SparcMEMrrAsmOperand;
|
||||
}
|
||||
def MEMri : Operand<iPTR> {
|
||||
let PrintMethod = "printMemOperand";
|
||||
let MIOperandInfo = (ops ptr_rc, i32imm);
|
||||
let ParserMatchClass = SparcMEMriAsmOperand;
|
||||
}
|
||||
|
||||
def TLSSym : Operand<iPTR>;
|
||||
|
|
@ -239,7 +251,10 @@ multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
|
|||
|
||||
// Pseudo instructions.
|
||||
class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
: InstSP<outs, ins, asmstr, pattern>;
|
||||
: InstSP<outs, ins, asmstr, pattern> {
|
||||
let isCodeGenOnly = 1;
|
||||
let isPseudo = 1;
|
||||
}
|
||||
|
||||
// GETPCX for PIC
|
||||
let Defs = [O7] in {
|
||||
|
|
@ -503,7 +518,7 @@ defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, i32imm>;
|
|||
defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, i32imm>;
|
||||
|
||||
// "LEA" forms of add (patterns to make tblgen happy)
|
||||
let Predicates = [Is32Bit] in
|
||||
let Predicates = [Is32Bit], isCodeGenOnly = 1 in
|
||||
def LEA_ADDri : F3_2<2, 0b000000,
|
||||
(outs IntRegs:$dst), (ins MEMri:$addr),
|
||||
"add ${addr:arith}, $dst",
|
||||
|
|
|
|||
Loading…
Reference in New Issue