forked from OSchip/llvm-project
[X86] Disable shouldFoldConstantShiftPairToMask for scalar shifts on AMD targets (PR40758)
D61068 handled vector shifts, this patch does the same for scalars where there are similar number of pipes for shifts as bit ops - this is true almost entirely for AMD targets where the scalar ALUs are well balanced. This combine avoids AND immediate mask which usually means we reduce encoding size. Some tests show use of (slow, scaled) LEA instead of SHL in some cases, but thats due to particular shift immediates - shift+mask generate these just as easily. Differential Revision: https://reviews.llvm.org/D61830 llvm-svn: 360684
This commit is contained in:
Simon Pilgrim
parent
3b917019a5
commit
c2d9cfd925
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@ -427,6 +427,11 @@ def FeatureFastHorizontalOps
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"Prefer horizontal vector math instructions (haddp, phsub, etc.) over "
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"normal vector instructions with shuffles", [FeatureSSE3]>;
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def FeatureFastScalarShiftMasks
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: SubtargetFeature<
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"fast-scalar-shift-masks", "HasFastScalarShiftMasks", "true",
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"Prefer a left/right scalar logical shift pair over a shift+and pair">;
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def FeatureFastVectorShiftMasks
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: SubtargetFeature<
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"fast-vector-shift-masks", "HasFastVectorShiftMasks", "true",
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@ -784,6 +789,7 @@ def ProcessorFeatures {
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FeatureSlowSHLD,
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FeatureLAHFSAHF,
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FeatureFast15ByteNOP,
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FeatureFastScalarShiftMasks,
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FeatureFastVectorShiftMasks];
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list<SubtargetFeature> BtVer1Features = BtVer1InheritableFeatures;
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@ -825,6 +831,7 @@ def ProcessorFeatures {
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FeatureSlowSHLD,
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FeatureLAHFSAHF,
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FeatureFast11ByteNOP,
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FeatureFastScalarShiftMasks,
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FeatureBranchFusion];
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list<SubtargetFeature> BdVer1Features = BdVer1InheritableFeatures;
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@ -876,6 +883,7 @@ def ProcessorFeatures {
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FeatureFastBEXTR,
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FeatureFast15ByteNOP,
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FeatureBranchFusion,
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FeatureFastScalarShiftMasks,
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FeatureMMX,
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FeatureMOVBE,
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FeatureMWAITX,
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@ -1092,20 +1100,22 @@ foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in {
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foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in {
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def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
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FeatureSSE2, Feature3DNowA, FeatureFXSR, FeatureNOPL,
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Feature64Bit, FeatureSlowSHLD, FeatureCMOV]>;
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Feature64Bit, FeatureSlowSHLD, FeatureCMOV,
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FeatureFastScalarShiftMasks]>;
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}
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foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in {
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def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureSSE3,
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Feature3DNowA, FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B,
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FeatureSlowSHLD, FeatureCMOV, Feature64Bit]>;
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FeatureSlowSHLD, FeatureCMOV, Feature64Bit,
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FeatureFastScalarShiftMasks]>;
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}
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foreach P = ["amdfam10", "barcelona"] in {
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def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureSSE4A, Feature3DNowA,
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FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B, FeatureLZCNT,
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FeaturePOPCNT, FeatureSlowSHLD, FeatureLAHFSAHF, FeatureCMOV,
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Feature64Bit]>;
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Feature64Bit, FeatureFastScalarShiftMasks]>;
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}
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// Bobcat
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@ -5021,11 +5021,12 @@ bool X86TargetLowering::shouldFoldConstantShiftPairToMask(
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(N->getOpcode() == ISD::SRL &&
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N->getOperand(0).getOpcode() == ISD::SHL)) &&
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"Expected shift-shift mask");
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if (Subtarget.hasFastVectorShiftMasks() && N->getValueType(0).isVector()) {
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EVT VT = N->getValueType(0);
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if ((Subtarget.hasFastVectorShiftMasks() && VT.isVector()) ||
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(Subtarget.hasFastScalarShiftMasks() && !VT.isVector())) {
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// Only fold if the shift values are equal - so it folds to AND.
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// TODO - we should fold if either is non-uniform but we don't do the
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// fold for non-splats yet.
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// TODO - we should fold if either is a non-uniform vector but we don't do
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// the fold for non-splats yet.
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return N->getOperand(1) == N->getOperand(0).getOperand(1);
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}
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return TargetLoweringBase::shouldFoldConstantShiftPairToMask(N, Level);
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@ -396,6 +396,9 @@ protected:
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/// Try harder to combine to horizontal vector ops if they are fast.
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bool HasFastHorizontalOps = false;
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/// Prefer a left/right scalar logical shifts pair over a shift+and pair.
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bool HasFastScalarShiftMasks = false;
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/// Prefer a left/right vector logical shifts pair over a shift+and pair.
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bool HasFastVectorShiftMasks = false;
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@ -650,6 +653,7 @@ public:
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bool hasFastSHLDRotate() const { return HasFastSHLDRotate; }
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bool hasFastBEXTR() const { return HasFastBEXTR; }
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bool hasFastHorizontalOps() const { return HasFastHorizontalOps; }
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bool hasFastScalarShiftMasks() const { return HasFastScalarShiftMasks; }
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bool hasFastVectorShiftMasks() const { return HasFastVectorShiftMasks; }
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bool hasMacroFusion() const { return HasMacroFusion; }
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bool hasBranchFusion() const { return HasBranchFusion; }
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@ -43,13 +43,21 @@ define i8 @test_i8_shl_lshr_1(i8 %a0) {
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; X86-NEXT: andb $-32, %al
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; X86-NEXT: retl
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;
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; X64-LABEL: test_i8_shl_lshr_1:
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; X64: # %bb.0:
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; X64-NEXT: # kill: def $edi killed $edi def $rdi
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; X64-NEXT: leal (,%rdi,4), %eax
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; X64-NEXT: andb $-32, %al
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; X64-NEXT: # kill: def $al killed $al killed $eax
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; X64-NEXT: retq
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; X64-MASK-LABEL: test_i8_shl_lshr_1:
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; X64-MASK: # %bb.0:
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; X64-MASK-NEXT: # kill: def $edi killed $edi def $rdi
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; X64-MASK-NEXT: leal (,%rdi,4), %eax
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; X64-MASK-NEXT: andb $-32, %al
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; X64-MASK-NEXT: # kill: def $al killed $al killed $eax
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; X64-MASK-NEXT: retq
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;
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; X64-SHIFT-LABEL: test_i8_shl_lshr_1:
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; X64-SHIFT: # %bb.0:
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; X64-SHIFT-NEXT: movl %edi, %eax
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; X64-SHIFT-NEXT: shrb $3, %al
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; X64-SHIFT-NEXT: shlb $5, %al
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; X64-SHIFT-NEXT: # kill: def $al killed $al killed $eax
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; X64-SHIFT-NEXT: retq
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%1 = lshr i8 %a0, 3
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%2 = shl i8 %1, 5
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ret i8 %2
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@ -63,13 +71,21 @@ define i8 @test_i8_shl_lshr_2(i8 %a0) {
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; X86-NEXT: andb $56, %al
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; X86-NEXT: retl
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;
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; X64-LABEL: test_i8_shl_lshr_2:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: shrb $2, %al
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; X64-NEXT: andb $56, %al
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; X64-NEXT: # kill: def $al killed $al killed $eax
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; X64-NEXT: retq
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; X64-MASK-LABEL: test_i8_shl_lshr_2:
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; X64-MASK: # %bb.0:
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; X64-MASK-NEXT: movl %edi, %eax
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; X64-MASK-NEXT: shrb $2, %al
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; X64-MASK-NEXT: andb $56, %al
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; X64-MASK-NEXT: # kill: def $al killed $al killed $eax
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; X64-MASK-NEXT: retq
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;
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; X64-SHIFT-LABEL: test_i8_shl_lshr_2:
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; X64-SHIFT: # %bb.0:
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; X64-SHIFT-NEXT: # kill: def $edi killed $edi def $rdi
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; X64-SHIFT-NEXT: shrb $5, %dil
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; X64-SHIFT-NEXT: leal (,%rdi,8), %eax
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; X64-SHIFT-NEXT: # kill: def $al killed $al killed $eax
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; X64-SHIFT-NEXT: retq
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%1 = lshr i8 %a0, 5
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%2 = shl i8 %1, 3
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ret i8 %2
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@ -103,13 +119,21 @@ define i16 @test_i16_shl_lshr_1(i16 %a0) {
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; X86-NEXT: # kill: def $ax killed $ax killed $eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test_i16_shl_lshr_1:
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; X64: # %bb.0:
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; X64-NEXT: # kill: def $edi killed $edi def $rdi
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; X64-NEXT: leal (,%rdi,4), %eax
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; X64-NEXT: andl $65504, %eax # imm = 0xFFE0
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; X64-NEXT: # kill: def $ax killed $ax killed $eax
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; X64-NEXT: retq
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; X64-MASK-LABEL: test_i16_shl_lshr_1:
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; X64-MASK: # %bb.0:
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; X64-MASK-NEXT: # kill: def $edi killed $edi def $rdi
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; X64-MASK-NEXT: leal (,%rdi,4), %eax
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; X64-MASK-NEXT: andl $65504, %eax # imm = 0xFFE0
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; X64-MASK-NEXT: # kill: def $ax killed $ax killed $eax
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; X64-MASK-NEXT: retq
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;
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; X64-SHIFT-LABEL: test_i16_shl_lshr_1:
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; X64-SHIFT: # %bb.0:
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; X64-SHIFT-NEXT: movzwl %di, %eax
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; X64-SHIFT-NEXT: shrl $3, %eax
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; X64-SHIFT-NEXT: shll $5, %eax
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; X64-SHIFT-NEXT: # kill: def $ax killed $ax killed $eax
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; X64-SHIFT-NEXT: retq
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%1 = lshr i16 %a0, 3
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%2 = shl i16 %1, 5
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ret i16 %2
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@ -124,13 +148,21 @@ define i16 @test_i16_shl_lshr_2(i16 %a0) {
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; X86-NEXT: # kill: def $ax killed $ax killed $eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test_i16_shl_lshr_2:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: shrl $2, %eax
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; X64-NEXT: andl $16376, %eax # imm = 0x3FF8
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; X64-NEXT: # kill: def $ax killed $ax killed $eax
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; X64-NEXT: retq
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; X64-MASK-LABEL: test_i16_shl_lshr_2:
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; X64-MASK: # %bb.0:
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; X64-MASK-NEXT: movl %edi, %eax
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; X64-MASK-NEXT: shrl $2, %eax
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; X64-MASK-NEXT: andl $16376, %eax # imm = 0x3FF8
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; X64-MASK-NEXT: # kill: def $ax killed $ax killed $eax
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; X64-MASK-NEXT: retq
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;
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; X64-SHIFT-LABEL: test_i16_shl_lshr_2:
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; X64-SHIFT: # %bb.0:
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; X64-SHIFT-NEXT: movzwl %di, %eax
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; X64-SHIFT-NEXT: shrl $5, %eax
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; X64-SHIFT-NEXT: shll $3, %eax
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; X64-SHIFT-NEXT: # kill: def $ax killed $ax killed $eax
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; X64-SHIFT-NEXT: retq
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%1 = lshr i16 %a0, 5
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%2 = shl i16 %1, 3
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ret i16 %2
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@ -161,12 +193,19 @@ define i32 @test_i32_shl_lshr_1(i32 %a0) {
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; X86-NEXT: andl $-32, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test_i32_shl_lshr_1:
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; X64: # %bb.0:
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; X64-NEXT: # kill: def $edi killed $edi def $rdi
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; X64-NEXT: leal (,%rdi,4), %eax
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; X64-NEXT: andl $-32, %eax
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; X64-NEXT: retq
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; X64-MASK-LABEL: test_i32_shl_lshr_1:
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; X64-MASK: # %bb.0:
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; X64-MASK-NEXT: # kill: def $edi killed $edi def $rdi
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; X64-MASK-NEXT: leal (,%rdi,4), %eax
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; X64-MASK-NEXT: andl $-32, %eax
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; X64-MASK-NEXT: retq
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;
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; X64-SHIFT-LABEL: test_i32_shl_lshr_1:
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; X64-SHIFT: # %bb.0:
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; X64-SHIFT-NEXT: movl %edi, %eax
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; X64-SHIFT-NEXT: shrl $3, %eax
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; X64-SHIFT-NEXT: shll $5, %eax
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; X64-SHIFT-NEXT: retq
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%1 = lshr i32 %a0, 3
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%2 = shl i32 %1, 5
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ret i32 %2
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@ -180,12 +219,19 @@ define i32 @test_i32_shl_lshr_2(i32 %a0) {
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; X86-NEXT: andl $-8, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test_i32_shl_lshr_2:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: shrl $2, %eax
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; X64-NEXT: andl $-8, %eax
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; X64-NEXT: retq
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; X64-MASK-LABEL: test_i32_shl_lshr_2:
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; X64-MASK: # %bb.0:
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; X64-MASK-NEXT: movl %edi, %eax
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; X64-MASK-NEXT: shrl $2, %eax
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; X64-MASK-NEXT: andl $-8, %eax
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; X64-MASK-NEXT: retq
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;
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; X64-SHIFT-LABEL: test_i32_shl_lshr_2:
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; X64-SHIFT: # %bb.0:
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; X64-SHIFT-NEXT: # kill: def $edi killed $edi def $rdi
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; X64-SHIFT-NEXT: shrl $5, %edi
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; X64-SHIFT-NEXT: leal (,%rdi,8), %eax
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; X64-SHIFT-NEXT: retq
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%1 = lshr i32 %a0, 5
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%2 = shl i32 %1, 3
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ret i32 %2
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@ -219,11 +265,18 @@ define i64 @test_i64_shl_lshr_1(i64 %a0) {
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; X86-NEXT: shldl $2, %ecx, %edx
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; X86-NEXT: retl
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;
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; X64-LABEL: test_i64_shl_lshr_1:
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; X64: # %bb.0:
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; X64-NEXT: leaq (,%rdi,4), %rax
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; X64-NEXT: andq $-32, %rax
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; X64-NEXT: retq
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; X64-MASK-LABEL: test_i64_shl_lshr_1:
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; X64-MASK: # %bb.0:
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; X64-MASK-NEXT: leaq (,%rdi,4), %rax
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; X64-MASK-NEXT: andq $-32, %rax
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; X64-MASK-NEXT: retq
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;
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; X64-SHIFT-LABEL: test_i64_shl_lshr_1:
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; X64-SHIFT: # %bb.0:
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; X64-SHIFT-NEXT: movq %rdi, %rax
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; X64-SHIFT-NEXT: shrq $3, %rax
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; X64-SHIFT-NEXT: shlq $5, %rax
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; X64-SHIFT-NEXT: retq
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%1 = lshr i64 %a0, 3
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%2 = shl i64 %1, 5
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ret i64 %2
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@ -239,12 +292,18 @@ define i64 @test_i64_shl_lshr_2(i64 %a0) {
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; X86-NEXT: shrl $2, %edx
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; X86-NEXT: retl
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;
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; X64-LABEL: test_i64_shl_lshr_2:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: shrq $2, %rax
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; X64-NEXT: andq $-8, %rax
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; X64-NEXT: retq
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; X64-MASK-LABEL: test_i64_shl_lshr_2:
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; X64-MASK: # %bb.0:
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; X64-MASK-NEXT: movq %rdi, %rax
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; X64-MASK-NEXT: shrq $2, %rax
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; X64-MASK-NEXT: andq $-8, %rax
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; X64-MASK-NEXT: retq
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;
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; X64-SHIFT-LABEL: test_i64_shl_lshr_2:
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; X64-SHIFT: # %bb.0:
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; X64-SHIFT-NEXT: shrq $5, %rdi
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; X64-SHIFT-NEXT: leaq (,%rdi,8), %rax
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; X64-SHIFT-NEXT: retq
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%1 = lshr i64 %a0, 5
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%2 = shl i64 %1, 3
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ret i64 %2
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