forked from OSchip/llvm-project
[MTE] Handle MTE instructions in AArch64LoadStoreOptimizer.
Summary: Generate pre- and post-indexed forms of ST*G and STGP when possible. Reviewers: ostannard, vitalybuka Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67741 llvm-svn: 372412
This commit is contained in:
parent
330014843c
commit
c2bda3e422
llvm
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@ -201,8 +201,22 @@ static bool isNarrowStore(unsigned Opc) {
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}
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}
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// These instruction set memory tag and either keep memory contents unchanged or
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// set it to zero, ignoring the address part of the source register.
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static bool isTagStore(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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default:
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return false;
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case AArch64::STGOffset:
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case AArch64::STZGOffset:
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case AArch64::ST2GOffset:
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case AArch64::STZ2GOffset:
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return true;
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}
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}
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// Scaling factor for unscaled load or store.
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static int getMemScale(MachineInstr &MI) {
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static int getMemScale(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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default:
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llvm_unreachable("Opcode has unknown scale!");
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@ -255,6 +269,11 @@ static int getMemScale(MachineInstr &MI) {
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case AArch64::STURQi:
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case AArch64::LDPQi:
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case AArch64::STPQi:
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case AArch64::STGOffset:
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case AArch64::STZGOffset:
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case AArch64::ST2GOffset:
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case AArch64::STZ2GOffset:
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case AArch64::STGPi:
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return 16;
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}
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}
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@ -449,6 +468,16 @@ static unsigned getPreIndexedOpcode(unsigned Opc) {
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return AArch64::STPWpre;
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case AArch64::STPXi:
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return AArch64::STPXpre;
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case AArch64::STGOffset:
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return AArch64::STGPreIndex;
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case AArch64::STZGOffset:
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return AArch64::STZGPreIndex;
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case AArch64::ST2GOffset:
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return AArch64::ST2GPreIndex;
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case AArch64::STZ2GOffset:
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return AArch64::STZ2GPreIndex;
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case AArch64::STGPi:
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return AArch64::STGPpre;
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}
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}
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@ -518,6 +547,16 @@ static unsigned getPostIndexedOpcode(unsigned Opc) {
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return AArch64::STPWpost;
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case AArch64::STPXi:
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return AArch64::STPXpost;
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case AArch64::STGOffset:
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return AArch64::STGPostIndex;
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case AArch64::STZGOffset:
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return AArch64::STZGPostIndex;
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case AArch64::ST2GOffset:
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return AArch64::ST2GPostIndex;
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case AArch64::STZ2GOffset:
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return AArch64::STZ2GPostIndex;
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case AArch64::STGPi:
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return AArch64::STGPpost;
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}
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}
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@ -536,10 +575,30 @@ static bool isPairedLdSt(const MachineInstr &MI) {
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case AArch64::STPQi:
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case AArch64::STPWi:
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case AArch64::STPXi:
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case AArch64::STGPi:
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return true;
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}
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}
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// Returns the scale and offset range of pre/post indexed variants of MI.
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static void getPrePostIndexedMemOpInfo(const MachineInstr &MI, int &Scale,
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int &MinOffset, int &MaxOffset) {
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bool IsPaired = isPairedLdSt(MI);
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bool IsTagStore = isTagStore(MI);
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// ST*G and all paired ldst have the same scale in pre/post-indexed variants
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// as in the "unsigned offset" variant.
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// All other pre/post indexed ldst instructions are unscaled.
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Scale = (IsTagStore || IsPaired) ? getMemScale(MI) : 1;
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if (IsPaired) {
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MinOffset = -64;
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MaxOffset = 63;
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} else {
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MinOffset = -256;
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MaxOffset = 255;
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}
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}
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static const MachineOperand &getLdStRegOp(const MachineInstr &MI,
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unsigned PairedRegOp = 0) {
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assert(PairedRegOp < 2 && "Unexpected register operand idx.");
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@ -618,6 +677,11 @@ static bool isMergeableLdStUpdate(MachineInstr &MI) {
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case AArch64::LDRWui:
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case AArch64::LDRHHui:
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case AArch64::LDRBBui:
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case AArch64::STGOffset:
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case AArch64::STZGOffset:
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case AArch64::ST2GOffset:
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case AArch64::STZ2GOffset:
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case AArch64::STGPi:
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// Unscaled instructions.
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case AArch64::STURSi:
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case AArch64::STURDi:
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@ -1328,18 +1392,19 @@ AArch64LoadStoreOpt::mergeUpdateInsn(MachineBasicBlock::iterator I,
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unsigned NewOpc = IsPreIdx ? getPreIndexedOpcode(I->getOpcode())
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: getPostIndexedOpcode(I->getOpcode());
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MachineInstrBuilder MIB;
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int Scale, MinOffset, MaxOffset;
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getPrePostIndexedMemOpInfo(*I, Scale, MinOffset, MaxOffset);
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if (!isPairedLdSt(*I)) {
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// Non-paired instruction.
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MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
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.add(getLdStRegOp(*Update))
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.add(getLdStRegOp(*I))
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.add(getLdStBaseOp(*I))
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.addImm(Value)
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.addImm(Value / Scale)
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.setMemRefs(I->memoperands())
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.setMIFlags(I->mergeFlagsWith(*Update));
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} else {
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// Paired instruction.
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int Scale = getMemScale(*I);
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MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
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.add(getLdStRegOp(*Update))
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.add(getLdStRegOp(*I, 0))
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@ -1395,28 +1460,21 @@ bool AArch64LoadStoreOpt::isMatchingUpdateInsn(MachineInstr &MemMI,
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MI.getOperand(1).getReg() != BaseReg)
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break;
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bool IsPairedInsn = isPairedLdSt(MemMI);
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int UpdateOffset = MI.getOperand(2).getImm();
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if (MI.getOpcode() == AArch64::SUBXri)
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UpdateOffset = -UpdateOffset;
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// For non-paired load/store instructions, the immediate must fit in a
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// signed 9-bit integer.
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if (!IsPairedInsn && (UpdateOffset > 255 || UpdateOffset < -256))
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// The immediate must be a multiple of the scaling factor of the pre/post
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// indexed instruction.
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int Scale, MinOffset, MaxOffset;
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getPrePostIndexedMemOpInfo(MemMI, Scale, MinOffset, MaxOffset);
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if (UpdateOffset % Scale != 0)
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break;
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// For paired load/store instructions, the immediate must be a multiple of
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// the scaling factor. The scaled offset must also fit into a signed 7-bit
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// integer.
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if (IsPairedInsn) {
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int Scale = getMemScale(MemMI);
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if (UpdateOffset % Scale != 0)
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break;
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int ScaledOffset = UpdateOffset / Scale;
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if (ScaledOffset > 63 || ScaledOffset < -64)
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break;
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}
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// Scaled offset must fit in the instruction immediate.
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int ScaledOffset = UpdateOffset / Scale;
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if (ScaledOffset > MaxOffset || ScaledOffset < MinOffset)
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break;
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// If we have a non-zero Offset, we check that it matches the amount
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// we're adding to the register.
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@ -1442,13 +1500,19 @@ MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnForward(
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if (MIUnscaledOffset != UnscaledOffset)
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return E;
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// If the base register overlaps a destination register, we can't
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// merge the update.
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bool IsPairedInsn = isPairedLdSt(MemMI);
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for (unsigned i = 0, e = IsPairedInsn ? 2 : 1; i != e; ++i) {
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Register DestReg = getLdStRegOp(MemMI, i).getReg();
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if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
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return E;
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// If the base register overlaps a source/destination register, we can't
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// merge the update. This does not apply to tag store instructions which
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// ignore the address part of the source register.
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// This does not apply to STGPi as well, which does not have unpredictable
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// behavior in this case unlike normal stores, and always performs writeback
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// after reading the source register value.
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if (!isTagStore(MemMI) && MemMI.getOpcode() != AArch64::STGPi) {
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bool IsPairedInsn = isPairedLdSt(MemMI);
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for (unsigned i = 0, e = IsPairedInsn ? 2 : 1; i != e; ++i) {
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Register DestReg = getLdStRegOp(MemMI, i).getReg();
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if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
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return E;
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}
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}
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// Track which register units have been modified and used between the first
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@ -1496,11 +1560,13 @@ MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnBackward(
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return E;
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// If the base register overlaps a destination register, we can't
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// merge the update.
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bool IsPairedInsn = isPairedLdSt(MemMI);
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for (unsigned i = 0, e = IsPairedInsn ? 2 : 1; i != e; ++i) {
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Register DestReg = getLdStRegOp(MemMI, i).getReg();
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if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
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return E;
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if (!isTagStore(MemMI)) {
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bool IsPairedInsn = isPairedLdSt(MemMI);
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for (unsigned i = 0, e = IsPairedInsn ? 2 : 1; i != e; ++i) {
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Register DestReg = getLdStRegOp(MemMI, i).getReg();
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if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
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return E;
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}
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}
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// Track which register units have been modified and used between the first
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@ -1659,7 +1725,7 @@ bool AArch64LoadStoreOpt::tryToMergeLdStUpdate
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// however, is not, so adjust here.
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int UnscaledOffset = getLdStOffsetOp(MI).getImm() * getMemScale(MI);
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// Look forward to try to find a post-index instruction. For example,
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// Look forward to try to find a pre-index instruction. For example,
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// ldr x1, [x0, #64]
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// add x0, x0, #64
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// merged into:
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@ -0,0 +1,285 @@
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# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass aarch64-ldst-opt -verify-machineinstrs -o - %s | FileCheck %s
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---
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### STG and its offset limits
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# CHECK-LABEL: name: test_STG_post
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# CHECK: STGPostIndex $x0, $x0, 7
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name: test_STG_post
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body: |
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bb.0.entry:
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liveins: $x0
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STGOffset $x0, $x0, 0
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$x0 = ADDXri $x0, 112, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_STG_post_same_reg
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# CHECK: STGPostIndex $x1, $x0, 7
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name: test_STG_post_same_reg
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body: |
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bb.0.entry:
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liveins: $x0, $x1
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STGOffset $x1, $x0, 0
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$x0 = ADDXri $x0, 112, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_STG_post_unaligned
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# CHECK: STGOffset $x0, $x0, 0
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# CHECK-NEXT: ADDXri $x0, 8, 0
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name: test_STG_post_unaligned
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body: |
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bb.0.entry:
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liveins: $x0
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STGOffset $x0, $x0, 0
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$x0 = ADDXri $x0, 8, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_STG_post2
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# CHECK: STGPostIndex $x0, $x0, -256
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name: test_STG_post2
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body: |
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bb.0.entry:
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liveins: $x0
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STGOffset $x0, $x0, 0
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$x0 = SUBXri $x0, 4096, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_STG_post3
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# CHECK: STGOffset $x0, $x0, 0
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# CHECK-NEXT: SUBXri $x0, 4112, 0
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name: test_STG_post3
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body: |
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bb.0.entry:
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liveins: $x0
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STGOffset $x0, $x0, 0
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$x0 = SUBXri $x0, 4112, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_STG_post4
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# CHECK: STGPostIndex $x0, $x0, 255
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name: test_STG_post4
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body: |
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bb.0.entry:
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liveins: $x0
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STGOffset $x0, $x0, 0
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$x0 = ADDXri $x0, 4080, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_STG_post5
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# CHECK: STGOffset $x0, $x0, 0
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# CHECK-NEXT: ADDXri $x0, 4096, 0
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name: test_STG_post5
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body: |
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bb.0.entry:
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liveins: $x0
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STGOffset $x0, $x0, 0
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$x0 = ADDXri $x0, 4096, 0
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RET_ReallyLR implicit $x0
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...
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### The rest of ST*G variants.
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# CHECK-LABEL: name: test_STZG_post
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# CHECK: STZGPostIndex $x0, $x0, 7
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name: test_STZG_post
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body: |
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bb.0.entry:
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liveins: $x0
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STZGOffset $x0, $x0, 0
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$x0 = ADDXri $x0, 112, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_ST2G_post
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# CHECK: ST2GPostIndex $x0, $x0, 7
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name: test_ST2G_post
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body: |
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bb.0.entry:
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liveins: $x0
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ST2GOffset $x0, $x0, 0
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$x0 = ADDXri $x0, 112, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_STZ2G_post
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# CHECK: STZ2GPostIndex $x0, $x0, 7
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name: test_STZ2G_post
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body: |
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bb.0.entry:
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liveins: $x0
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STZ2GOffset $x0, $x0, 0
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$x0 = ADDXri $x0, 112, 0
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RET_ReallyLR implicit $x0
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...
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### STGP and its offset limits
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# CHECK-LABEL: name: test_STGP_post
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# CHECK: STGPpost $x1, $x2, $x0, 7
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name: test_STGP_post
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body: |
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bb.0.entry:
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liveins: $x0, $x1, $x2
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STGPi $x1, $x2, $x0, 0
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$x0 = ADDXri $x0, 112, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_STGP_post2
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# CHECK: STGPpost $x1, $x2, $x0, -64
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name: test_STGP_post2
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body: |
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bb.0.entry:
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liveins: $x0, $x1, $x2
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STGPi $x1, $x2, $x0, 0
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$x0 = SUBXri $x0, 1024, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_STGP_post3
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# CHECK: STGPi $x1, $x2, $x0, 0
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# CHECK-NEXT: SUBXri $x0, 1040, 0
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name: test_STGP_post3
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body: |
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bb.0.entry:
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liveins: $x0, $x1, $x2
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STGPi $x1, $x2, $x0, 0
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$x0 = SUBXri $x0, 1040, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_STGP_post4
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# CHECK: STGPpost $x1, $x2, $x0, 63
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name: test_STGP_post4
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body: |
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bb.0.entry:
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liveins: $x0, $x1, $x2
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STGPi $x1, $x2, $x0, 0
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$x0 = ADDXri $x0, 1008, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_STGP_post5
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# CHECK: STGPi $x1, $x2, $x0, 0
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# CHECK-NEXT: ADDXri $x0, 1024, 0
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name: test_STGP_post5
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body: |
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bb.0.entry:
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liveins: $x0, $x1, $x2
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STGPi $x1, $x2, $x0, 0
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$x0 = ADDXri $x0, 1024, 0
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RET_ReallyLR implicit $x0
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...
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### Pre-indexed forms
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# CHECK-LABEL: name: test_STG_pre
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# CHECK: STGPreIndex $x0, $x0, 10
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name: test_STG_pre
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body: |
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bb.0.entry:
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liveins: $x0
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STGOffset $x0, $x0, 10
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$x0 = ADDXri $x0, 160, 0
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RET_ReallyLR implicit $x0
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...
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# CHECK-LABEL: name: test_STGP_pre
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# CHECK: STGPpre $x1, $x2, $x0, 10
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name: test_STGP_pre
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $x0, $x1, $x2
|
||||
|
||||
STGPi $x1, $x2, $x0, 10
|
||||
$x0 = ADDXri $x0, 160, 0
|
||||
RET_ReallyLR implicit $x0
|
||||
...
|
||||
|
||||
### Pre-indexed forms with add/sub coming before the store.
|
||||
|
||||
# CHECK-LABEL: name: test_STG_pre_back
|
||||
# CHECK: STGPreIndex $x0, $x0, 2
|
||||
name: test_STG_pre_back
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $x0
|
||||
|
||||
$x0 = ADDXri $x0, 32, 0
|
||||
STGOffset $x0, $x0, 0
|
||||
RET_ReallyLR implicit $x0
|
||||
...
|
||||
|
||||
# CHECK-LABEL: name: test_STGP_pre_back
|
||||
# CHECK: STGPpre $x1, $x2, $x0, -3
|
||||
name: test_STGP_pre_back
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $x0, $x1, $x2
|
||||
|
||||
$x0 = SUBXri $x0, 48, 0
|
||||
STGPi $x1, $x2, $x0, 0
|
||||
RET_ReallyLR implicit $x0
|
||||
...
|
||||
|
||||
### STGP with source register == address register
|
||||
|
||||
# CHECK-LABEL: name: test_STGP_post_same_reg
|
||||
# CHECK: STGPpost $x0, $x0, $x0, 7
|
||||
name: test_STGP_post_same_reg
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $x0
|
||||
|
||||
STGPi $x0, $x0, $x0, 0
|
||||
$x0 = ADDXri $x0, 112, 0
|
||||
RET_ReallyLR implicit $x0
|
||||
...
|
||||
|
||||
# CHECK-LABEL: name: test_STGP_pre_same_reg
|
||||
# CHECK: STGPpre $x0, $x0, $x0, 7
|
||||
name: test_STGP_pre_same_reg
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $x0
|
||||
|
||||
STGPi $x0, $x0, $x0, 7
|
||||
$x0 = ADDXri $x0, 112, 0
|
||||
RET_ReallyLR implicit $x0
|
||||
...
|
||||
|
||||
# This case can not be merged because the source register is always read before writeback.
|
||||
# CHECK-LABEL: name: test_STGP_pre_back_same_reg
|
||||
# CHECK: SUBXri $x0, 48, 0
|
||||
# CHECK-NEXT: STGPi $x0, $x0, $x0, 0
|
||||
name: test_STGP_pre_back_same_reg
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $x0
|
||||
|
||||
$x0 = SUBXri $x0, 48, 0
|
||||
STGPi $x0, $x0, $x0, 0
|
||||
RET_ReallyLR implicit $x0
|
||||
...
|
|
@ -65,7 +65,7 @@ entry:
|
|||
define void @stgp_alloca(i64 %a, i64 %b) {
|
||||
entry:
|
||||
; CHECK-LABEL: stgp_alloca:
|
||||
; CHECK: stgp x0, x1, [sp]
|
||||
; CHECK: stgp x0, x1, [sp, #-32]!
|
||||
; CHECK: stgp x1, x0, [sp, #16]
|
||||
; CHECK: ret
|
||||
%x = alloca i8, i32 32, align 16
|
||||
|
|
Loading…
Reference in New Issue