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[AArch64] Add the constraint to NEON scalar mla/mls instructions. 

llvm-svn: 193118
This commit is contained in:
Chad Rosier 2013-10-21 20:12:01 +00:00
parent e012cb3783
commit c2a0b13c25
2 changed files with 10 additions and 10 deletions
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4
clang/include/clang/Basic/arm_neon.td
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@ -882,11 +882,11 @@ def SCALAR_USQADD : SInst<"vsqadd", "sss", "SUcSUsSUiSUl">;
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Signed Saturating Doubling Multiply-Add Long // Signed Saturating Doubling Multiply-Add Long
def SCALAR_SQDMLAL : SInst<"vqdmlal", "rss", "SsSi">; def SCALAR_SQDMLAL : SInst<"vqdmlal", "rrss", "SsSi">;
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Signed Saturating Doubling Multiply-Subtract Long // Signed Saturating Doubling Multiply-Subtract Long
def SCALAR_SQDMLSL : SInst<"vqdmlsl", "rss", "SsSi">; def SCALAR_SQDMLSL : SInst<"vqdmlsl", "rrss", "SsSi">;
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Signed Saturating Doubling Multiply Long // Signed Saturating Doubling Multiply Long

16
clang/test/CodeGen/aarch64-neon-intrinsics.c
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@ -7226,28 +7226,28 @@ uint64_t test_vsqaddd_u64(uint64_t a, uint64_t b) {
return (uint64_t)vsqaddd_u64(a, b); return (uint64_t)vsqaddd_u64(a, b);
} }
int32_t test_vqdmlalh_s16(int16_t a, int16_t b) { int32_t test_vqdmlalh_s16(int32_t a, int16_t b, int16_t c) {
// CHECK: test_vqdmlalh_s16 // CHECK: test_vqdmlalh_s16
// CHECK: sqdmlal {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}} // CHECK: sqdmlal {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
return (int32_t)vqdmlalh_s16(a, b); return (int32_t)vqdmlalh_s16(a, b, c);
} }
int64_t test_vqdmlals_s32(int32_t a, int32_t b) { int64_t test_vqdmlals_s32(int64_t a, int32_t b, int32_t c) {
// CHECK: test_vqdmlals_s32 // CHECK: test_vqdmlals_s32
// CHECK: sqdmlal {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} // CHECK: sqdmlal {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
return (int64_t)vqdmlals_s32(a, b); return (int64_t)vqdmlals_s32(a, b, c);
} }
int32_t test_vqdmlslh_s16(int16_t a, int16_t b) { int32_t test_vqdmlslh_s16(int32_t a, int16_t b, int16_t c) {
// CHECK: test_vqdmlslh_s16 // CHECK: test_vqdmlslh_s16
// CHECK: sqdmlsl {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}} // CHECK: sqdmlsl {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
return (int32_t)vqdmlslh_s16(a, b); return (int32_t)vqdmlslh_s16(a, b, c);
} }
int64_t test_vqdmlsls_s32(int32_t a, int32_t b) { int64_t test_vqdmlsls_s32(int64_t a, int32_t b, int32_t c) {
// CHECK: test_vqdmlsls_s32 // CHECK: test_vqdmlsls_s32
// CHECK: sqdmlsl {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} // CHECK: sqdmlsl {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
return (int64_t)vqdmlsls_s32(a, b); return (int64_t)vqdmlsls_s32(a, b, c);
} }
int32_t test_vqdmullh_s16(int16_t a, int16_t b) { int32_t test_vqdmullh_s16(int16_t a, int16_t b) {