forked from OSchip/llvm-project
[PPC CodeGen] Expand the bitreverse.i32 intrinsic.
Differential Revision: https://reviews.llvm.org/D33572 Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093 llvm-svn: 307413
This commit is contained in:
Tony Jiang
parent
6687318bab
commit
c260e0eb56
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@ -136,6 +136,9 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
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}
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// Match BITREVERSE to customized fast code sequence in the td file.
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setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
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// PowerPC has an i16 but no i8 (or i1) SEXTLOAD.
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for (MVT VT : MVT::integer_valuetypes()) {
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setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
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@ -4454,3 +4454,71 @@ def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>;
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def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>;
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} // IsISA3_0
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// Fast 32-bit reverse bits algorithm:
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// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit):
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// n = ((n >> 1) & 0x55555555) | ((n << 1) & 0xAAAAAAAA);
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// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit):
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// n = ((n >> 2) & 0x33333333) | ((n << 2) & 0xCCCCCCCC);
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// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit):
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// n = ((n >> 4) & 0x0F0F0F0F) | ((n << 4) & 0xF0F0F0F0);
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// Step 4: byte reverse (Suppose n = [B1,B2,B3,B4]):
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// Step 4.1: Put B4,B2 in the right position (rotate left 3 bytes):
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// n' = (n rotl 24); After which n' = [B4, B1, B2, B3]
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// Step 4.2: Insert B3 to the right position:
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// n' = rlwimi n', n, 8, 8, 15; After which n' = [B4, B3, B2, B3]
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// Step 4.3: Insert B1 to the right position:
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// n' = rlwimi n', n, 8, 24, 31; After which n' = [B4, B3, B2, B1]
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def MaskValues {
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dag Lo1 = (ORI (LIS 0x5555), 0x5555);
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dag Hi1 = (ORI (LIS 0xAAAA), 0xAAAA);
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dag Lo2 = (ORI (LIS 0x3333), 0x3333);
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dag Hi2 = (ORI (LIS 0xCCCC), 0xCCCC);
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dag Lo4 = (ORI (LIS 0x0F0F), 0x0F0F);
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dag Hi4 = (ORI (LIS 0xF0F0), 0xF0F0);
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}
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def Shift1 {
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dag Right = (RLWINM $A, 31, 1, 31);
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dag Left = (RLWINM $A, 1, 0, 30);
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}
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def Swap1 {
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dag Bit = (OR (AND Shift1.Right, MaskValues.Lo1),
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(AND Shift1.Left, MaskValues.Hi1));
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}
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def Shift2 {
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dag Right = (RLWINM Swap1.Bit, 30, 2, 31);
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dag Left = (RLWINM Swap1.Bit, 2, 0, 29);
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}
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def Swap2 {
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dag Bits = (OR (AND Shift2.Right, MaskValues.Lo2),
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(AND Shift2.Left, MaskValues.Hi2));
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}
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def Shift4 {
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dag Right = (RLWINM Swap2.Bits, 28, 4, 31);
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dag Left = (RLWINM Swap2.Bits, 4, 0, 27);
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}
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def Swap4 {
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dag Bits = (OR (AND Shift4.Right, MaskValues.Lo4),
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(AND Shift4.Left, MaskValues.Hi4));
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}
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def Rotate {
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dag Left3Bytes = (RLWINM Swap4.Bits, 24, 0, 31);
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}
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def RotateInsertByte3 {
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dag Left = (RLWIMI Rotate.Left3Bytes, Swap4.Bits, 8, 8, 15);
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}
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def RotateInsertByte1 {
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dag Left = (RLWIMI RotateInsertByte3.Left, Swap4.Bits, 8, 24, 31);
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}
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def : Pat<(i32 (bitreverse i32:$A)),
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(RLDICL_32 RotateInsertByte1.Left, 0, 32)>;
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@ -1,23 +0,0 @@
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; RUN: llc -verify-machineinstrs -march=ppc64 %s -o - | FileCheck %s
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; These tests just check that the plumbing is in place for @llvm.bitreverse. The
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; actual output is massive at the moment as llvm.bitreverse is not yet legal.
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declare <2 x i16> @llvm.bitreverse.v2i16(<2 x i16>) readnone
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define <2 x i16> @f(<2 x i16> %a) {
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; CHECK-LABEL: f:
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; CHECK: rlwinm
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%b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a)
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ret <2 x i16> %b
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}
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declare i8 @llvm.bitreverse.i8(i8) readnone
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define i8 @g(i8 %a) {
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; CHECK-LABEL: g:
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; CHECK: rlwinm
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; CHECK: rlwimi
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%b = call i8 @llvm.bitreverse.i8(i8 %a)
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ret i8 %b
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}
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@ -0,0 +1,67 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
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define zeroext i32 @ReverseBits(i32 zeroext %n) {
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; CHECK-LABEL: ReverseBits:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: lis 4, -21846
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; CHECK-NEXT: lis 5, 21845
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; CHECK-NEXT: slwi 6, 3, 1
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; CHECK-NEXT: srwi 3, 3, 1
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; CHECK-NEXT: lis 7, -13108
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; CHECK-NEXT: lis 8, 13107
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; CHECK-NEXT: ori 4, 4, 43690
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; CHECK-NEXT: ori 5, 5, 21845
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; CHECK-NEXT: lis 10, -3856
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; CHECK-NEXT: lis 11, 3855
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; CHECK-NEXT: and 3, 3, 5
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; CHECK-NEXT: and 4, 6, 4
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; CHECK-NEXT: ori 5, 8, 13107
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: ori 4, 7, 52428
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; CHECK-NEXT: slwi 9, 3, 2
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; CHECK-NEXT: srwi 3, 3, 2
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; CHECK-NEXT: and 3, 3, 5
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; CHECK-NEXT: and 4, 9, 4
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; CHECK-NEXT: ori 5, 11, 3855
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: ori 4, 10, 61680
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; CHECK-NEXT: slwi 12, 3, 4
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; CHECK-NEXT: srwi 3, 3, 4
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; CHECK-NEXT: and 4, 12, 4
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; CHECK-NEXT: and 3, 3, 5
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: rotlwi 4, 3, 24
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; CHECK-NEXT: rlwimi 4, 3, 8, 8, 15
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; CHECK-NEXT: rlwimi 4, 3, 8, 24, 31
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; CHECK-NEXT: rldicl 3, 4, 0, 32
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; CHECK-NEXT: clrldi 3, 3, 32
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; CHECK-NEXT: blr
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entry:
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%shr = lshr i32 %n, 1
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%and = and i32 %shr, 1431655765
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%and1 = shl i32 %n, 1
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%shl = and i32 %and1, -1431655766
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%or = or i32 %and, %shl
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%shr2 = lshr i32 %or, 2
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%and3 = and i32 %shr2, 858993459
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%and4 = shl i32 %or, 2
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%shl5 = and i32 %and4, -858993460
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%or6 = or i32 %and3, %shl5
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%shr7 = lshr i32 %or6, 4
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%and8 = and i32 %shr7, 252645135
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%and9 = shl i32 %or6, 4
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%shl10 = and i32 %and9, -252645136
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%or11 = or i32 %and8, %shl10
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%shr13 = lshr i32 %or11, 24
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%and14 = lshr i32 %or11, 8
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%shr15 = and i32 %and14, 65280
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%and17 = shl i32 %or11, 8
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%shl18 = and i32 %and17, 16711680
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%shl21 = shl i32 %or11, 24
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%or16 = or i32 %shl21, %shr13
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%or19 = or i32 %or16, %shr15
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%or22 = or i32 %or19, %shl18
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ret i32 %or22
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}
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@ -0,0 +1,42 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
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declare i32 @llvm.bitreverse.i32(i32)
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define i32 @testBitReverseIntrinsicI32(i32 %arg) {
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; CHECK-LABEL: testBitReverseIntrinsicI32:
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; CHECK: # BB#0:
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; CHECK-NEXT: lis 4, -21846
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; CHECK-NEXT: lis 5, 21845
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; CHECK-NEXT: slwi 6, 3, 1
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; CHECK-NEXT: srwi 3, 3, 1
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; CHECK-NEXT: lis 7, -13108
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; CHECK-NEXT: lis 8, 13107
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; CHECK-NEXT: ori 4, 4, 43690
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; CHECK-NEXT: ori 5, 5, 21845
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; CHECK-NEXT: lis 10, -3856
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; CHECK-NEXT: lis 11, 3855
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; CHECK-NEXT: and 3, 3, 5
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; CHECK-NEXT: and 4, 6, 4
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; CHECK-NEXT: ori 5, 8, 13107
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: ori 4, 7, 52428
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; CHECK-NEXT: slwi 9, 3, 2
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; CHECK-NEXT: srwi 3, 3, 2
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; CHECK-NEXT: and 3, 3, 5
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; CHECK-NEXT: and 4, 9, 4
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; CHECK-NEXT: ori 5, 11, 3855
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: ori 4, 10, 61680
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; CHECK-NEXT: slwi 12, 3, 4
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; CHECK-NEXT: srwi 3, 3, 4
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; CHECK-NEXT: and 4, 12, 4
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; CHECK-NEXT: and 3, 3, 5
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: rotlwi 4, 3, 24
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; CHECK-NEXT: rlwimi 4, 3, 8, 8, 15
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; CHECK-NEXT: rlwimi 4, 3, 8, 24, 31
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; CHECK-NEXT: rldicl 3, 4, 0, 32
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; CHECK-NEXT: blr
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%res = call i32 @llvm.bitreverse.i32(i32 %arg)
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ret i32 %res
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}
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