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[ARM] Make ARMExpandPseudo add implicit uses for predicated instructions 

Missing these could potentially screw up post-ra scheduling.

Issue found by inspection, so I don't have a real testcase. Included
test just verifies the expected operands after expansion.

Differential Revision: https://reviews.llvm.org/D35156

llvm-svn: 312589
This commit is contained in:
Eli Friedman 2017-09-05 22:54:06 +00:00
parent 06d0ee734a
commit c22c699882
2 changed files with 101 additions and 8 deletions
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34
llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
View File

@ -664,6 +664,12 @@ static bool IsAnAddressOperand(const MachineOperand &MO) {
llvm_unreachable("unhandled machine operand type");
}
static MachineOperand makeImplicit(const MachineOperand &MO) {
MachineOperand NewMO = MO;
NewMO.setImplicit();
return NewMO;
}
void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI) {
MachineInstr &MI = *MBBI;
@ -698,6 +704,8 @@ void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
LO16.addImm(Pred).addReg(PredReg).add(condCodeOp());
HI16.addImm(Pred).addReg(PredReg).add(condCodeOp());
if (isCC)
LO16.add(makeImplicit(MI.getOperand(1)));
TransferImpOps(MI, LO16, HI16);
MI.eraseFromParent();
return;
@ -751,6 +759,8 @@ void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
if (RequiresBundling)
finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator());
if (isCC)
LO16.add(makeImplicit(MI.getOperand(1)));
TransferImpOps(MI, LO16, HI16);
MI.eraseFromParent();
}
@ -1052,7 +1062,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
MI.getOperand(1).getReg())
.add(MI.getOperand(2))
.addImm(MI.getOperand(3).getImm()) // 'pred'
.add(MI.getOperand(4));
.add(MI.getOperand(4))
.add(makeImplicit(MI.getOperand(1)));
MI.eraseFromParent();
return true;
@ -1065,7 +1076,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
.add(MI.getOperand(2))
.addImm(MI.getOperand(3).getImm()) // 'pred'
.add(MI.getOperand(4))
.add(condCodeOp()); // 's' bit
.add(condCodeOp()) // 's' bit
.add(makeImplicit(MI.getOperand(1)));
MI.eraseFromParent();
return true;
@ -1077,7 +1089,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
.addImm(MI.getOperand(3).getImm())
.addImm(MI.getOperand(4).getImm()) // 'pred'
.add(MI.getOperand(5))
.add(condCodeOp()); // 's' bit
.add(condCodeOp()) // 's' bit
.add(makeImplicit(MI.getOperand(1)));
MI.eraseFromParent();
return true;
@ -1090,7 +1103,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
.addImm(MI.getOperand(4).getImm())
.addImm(MI.getOperand(5).getImm()) // 'pred'
.add(MI.getOperand(6))
.add(condCodeOp()); // 's' bit
.add(condCodeOp()) // 's' bit
.add(makeImplicit(MI.getOperand(1)));
MI.eraseFromParent();
return true;
@ -1102,7 +1116,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
MI.getOperand(1).getReg())
.addImm(MI.getOperand(2).getImm())
.addImm(MI.getOperand(3).getImm()) // 'pred'
.add(MI.getOperand(4));
.add(MI.getOperand(4))
.add(makeImplicit(MI.getOperand(1)));
MI.eraseFromParent();
return true;
}
@ -1114,7 +1129,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
.addImm(MI.getOperand(2).getImm())
.addImm(MI.getOperand(3).getImm()) // 'pred'
.add(MI.getOperand(4))
.add(condCodeOp()); // 's' bit
.add(condCodeOp()) // 's' bit
.add(makeImplicit(MI.getOperand(1)));
MI.eraseFromParent();
return true;
@ -1127,7 +1143,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
.addImm(MI.getOperand(2).getImm())
.addImm(MI.getOperand(3).getImm()) // 'pred'
.add(MI.getOperand(4))
.add(condCodeOp()); // 's' bit
.add(condCodeOp()) // 's' bit
.add(makeImplicit(MI.getOperand(1)));
MI.eraseFromParent();
return true;
@ -1150,7 +1167,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
.addImm(MI.getOperand(3).getImm())
.addImm(MI.getOperand(4).getImm()) // 'pred'
.add(MI.getOperand(5))
.add(condCodeOp()); // 's' bit
.add(condCodeOp()) // 's' bit
.add(makeImplicit(MI.getOperand(1)));
MI.eraseFromParent();
return true;
}

75
llvm/test/CodeGen/ARM/expand-pseudos.mir Normal file
View File

@ -0,0 +1,75 @@
# RUN: llc -run-pass=arm-pseudo -verify-machineinstrs %s -o - | FileCheck %s
--- |
target triple = "armv7---gnueabi"
define i32 @test1(i32 %x) {
entry:
unreachable
}
define i32 @test2(i32 %x) {
entry:
unreachable
}
define i32 @test3(i32 %x) {
entry:
unreachable
}
...
---
name: test1
alignment: 2
tracksRegLiveness: true
liveins:
- { reg: '%r0', virtual-reg: '' }
body: |
bb.0.entry:
liveins: %r0
%r1 = MOVi 2, 14, _, _
CMPri killed %r0, 0, 14, _, implicit-def %cpsr
%r1 = MOVCCi16 killed %r1, 500, 0, killed %cpsr
%r0 = MOVr killed %r1, 14, _, _
BX_RET 14, _, implicit %r0
...
---
name: test2
alignment: 2
tracksRegLiveness: true
liveins:
- { reg: '%r0', virtual-reg: '' }
body: |
bb.0.entry:
liveins: %r0
%r1 = MOVi 2, 14, _, _
CMPri killed %r0, 0, 14, _, implicit-def %cpsr
%r1 = MOVCCi32imm killed %r1, 500500500, 0, killed %cpsr
%r0 = MOVr killed %r1, 14, _, _
BX_RET 14, _, implicit %r0
...
---
name: test3
alignment: 2
tracksRegLiveness: true
liveins:
- { reg: '%r0', virtual-reg: '' }
- { reg: '%r1', virtual-reg: '' }
body: |
bb.0.entry:
liveins: %r0, %r1
CMPri %r1, 500, 14, _, implicit-def %cpsr
%r0 = MOVCCr killed %r0, killed %r1, 12, killed %cpsr
BX_RET 14, _, implicit %r0
...
# CHECK-LABEL: name: test1
# CHECK: %r1 = MOVi16 500, 0, killed %cpsr, implicit killed %r1
# CHECK-LABEL: name: test2
# CHECK: %r1 = MOVi16 2068, 0, %cpsr, implicit killed %r1
# CHECK: %r1 = MOVTi16 %r1, 7637, 0, %cpsr
# CHECK-LABEL: name: test3
# CHECK: %r0 = MOVr killed %r1, 12, killed %cpsr, _, implicit killed %r0