forked from OSchip/llvm-project
[Hexagon] Implement vector-pair zero as V6_vsubw_dv
llvm-svn: 334123
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@ -1153,6 +1153,14 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
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MBB.erase(MI);
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MBB.erase(MI);
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return true;
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return true;
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}
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}
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case Hexagon::PS_vdd0: {
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unsigned Vd = MI.getOperand(0).getReg();
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BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd)
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.addReg(Vd, RegState::Undef)
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.addReg(Vd, RegState::Undef);
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MBB.erase(MI);
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return true;
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}
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case Hexagon::PS_vmulw: {
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case Hexagon::PS_vmulw: {
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// Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
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// Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
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unsigned DstReg = MI.getOperand(0).getReg();
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unsigned DstReg = MI.getOperand(0).getReg();
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@ -185,10 +185,13 @@ let Predicates = [UseHVX] in {
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def: Pat<(VecI8 vzero), (V6_vd0)>;
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def: Pat<(VecI8 vzero), (V6_vd0)>;
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def: Pat<(VecI16 vzero), (V6_vd0)>;
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def: Pat<(VecI16 vzero), (V6_vd0)>;
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def: Pat<(VecI32 vzero), (V6_vd0)>;
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def: Pat<(VecI32 vzero), (V6_vd0)>;
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// Use V6_vsubw_dv instead.
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def: Pat<(VecPI8 vzero), (PS_vdd0)>;
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def: Pat<(VecPI8 vzero), (Combinev (V6_vd0), (V6_vd0))>;
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def: Pat<(VecPI16 vzero), (PS_vdd0)>;
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def: Pat<(VecPI16 vzero), (Combinev (V6_vd0), (V6_vd0))>;
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def: Pat<(VecPI32 vzero), (PS_vdd0)>;
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def: Pat<(VecPI32 vzero), (Combinev (V6_vd0), (V6_vd0))>;
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def: Pat<(concat_vectors (VecI8 vzero), (VecI8 vzero)), (PS_vdd0)>;
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def: Pat<(concat_vectors (VecI16 vzero), (VecI16 vzero)), (PS_vdd0)>;
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def: Pat<(concat_vectors (VecI32 vzero), (VecI32 vzero)), (PS_vdd0)>;
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def: Pat<(VecPI8 (concat_vectors HVI8:$Vs, HVI8:$Vt)),
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def: Pat<(VecPI8 (concat_vectors HVI8:$Vs, HVI8:$Vt)),
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(Combinev HvxVR:$Vt, HvxVR:$Vs)>;
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(Combinev HvxVR:$Vt, HvxVR:$Vs)>;
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@ -461,6 +461,8 @@ let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
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V6_veqw.Itinerary, TypeCVI_VA>;
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V6_veqw.Itinerary, TypeCVI_VA>;
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def PS_qfalse: InstHexagon<(outs HvxQR:$Qd), (ins), "", [], "",
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def PS_qfalse: InstHexagon<(outs HvxQR:$Qd), (ins), "", [], "",
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V6_vgtw.Itinerary, TypeCVI_VA>;
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V6_vgtw.Itinerary, TypeCVI_VA>;
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def PS_vdd0: InstHexagon<(outs HvxWR:$Vd), (ins), "", [], "",
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V6_vsubw_dv.Itinerary, TypeCVI_VA_DV>;
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}
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}
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// Store predicate.
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// Store predicate.
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@ -0,0 +1,41 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK-LABEL: f0:
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; CHECK: v1:0.w = vsub(v1:0.w,v1:0.w)
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define <128 x i8> @f0() #0 {
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ret <128 x i8> zeroinitializer
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}
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; CHECK-LABEL: f1:
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; CHECK: v1:0.w = vsub(v1:0.w,v1:0.w)
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define <64 x i16> @f1() #0 {
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ret <64 x i16> zeroinitializer
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}
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; CHECK-LABEL: f2:
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; CHECK: v1:0.w = vsub(v1:0.w,v1:0.w)
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define <32 x i32> @f2() #0 {
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ret <32 x i32> zeroinitializer
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}
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; CHECK-LABEL: f3:
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; CHECK: v1:0.w = vsub(v1:0.w,v1:0.w)
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define <256 x i8> @f3() #1 {
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ret <256 x i8> zeroinitializer
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}
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; CHECK-LABEL: f4:
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; CHECK: v1:0.w = vsub(v1:0.w,v1:0.w)
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define <128 x i16> @f4() #1 {
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ret <128 x i16> zeroinitializer
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}
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; CHECK-LABEL: f5:
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; CHECK: v1:0.w = vsub(v1:0.w,v1:0.w)
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define <64 x i32> @f5() #1 {
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ret <64 x i32> zeroinitializer
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}
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attributes #0 = { readnone nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
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attributes #1 = { readnone nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
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