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[InstSimplify] Add tests for missed optimizations in simplifyUnsignedRangeCheck (NFC) 

These are the baseline tests for the functional change in D47922.

Patch by Li Jia He!

Differential Revision: https://reviews.llvm.org/D48000

llvm-svn: 335128
This commit is contained in:
Sanjay Patel 2018-06-20 14:03:13 +00:00
parent 79d2b50ca8
commit c1d2177f9d
1 changed files with 67 additions and 2 deletions
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69
llvm/test/Transforms/InstSimplify/AndOrXor.ll
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@ -374,6 +374,19 @@ define i1 @and_icmp1(i32 %x, i32 %y) {
define i1 @and_icmp2(i32 %x, i32 %y) { define i1 @and_icmp2(i32 %x, i32 %y) {
; CHECK-LABEL: @and_icmp2( ; CHECK-LABEL: @and_icmp2(
; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[X]], 0
; CHECK-NEXT: [[TMP3:%.*]] = and i1 [[TMP1]], [[TMP2]]
; CHECK-NEXT: ret i1 [[TMP3]]
;
%1 = icmp ugt i32 %x, %y
%2 = icmp ne i32 %x, 0
%3 = and i1 %1, %2
ret i1 %3
}
define i1 @and_icmp3(i32 %x, i32 %y) {
; CHECK-LABEL: @and_icmp3(
; CHECK-NEXT: ret i1 false ; CHECK-NEXT: ret i1 false
; ;
%1 = icmp ult i32 %x, %y %1 = icmp ult i32 %x, %y
@ -382,6 +395,19 @@ define i1 @and_icmp2(i32 %x, i32 %y) {
ret i1 %3 ret i1 %3
} }
define i1 @and_icmp4(i32 %x, i32 %y) {
; CHECK-LABEL: @and_icmp4(
; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[X]], 0
; CHECK-NEXT: [[TMP3:%.*]] = and i1 [[TMP1]], [[TMP2]]
; CHECK-NEXT: ret i1 [[TMP3]]
;
%1 = icmp ugt i32 %x, %y
%2 = icmp eq i32 %x, 0
%3 = and i1 %1, %2
ret i1 %3
}
define i1 @or_icmp1(i32 %x, i32 %y) { define i1 @or_icmp1(i32 %x, i32 %y) {
; CHECK-LABEL: @or_icmp1( ; CHECK-LABEL: @or_icmp1(
; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[Y:%.*]], 0 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[Y:%.*]], 0
@ -395,6 +421,19 @@ define i1 @or_icmp1(i32 %x, i32 %y) {
define i1 @or_icmp2(i32 %x, i32 %y) { define i1 @or_icmp2(i32 %x, i32 %y) {
; CHECK-LABEL: @or_icmp2( ; CHECK-LABEL: @or_icmp2(
; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[X]], 0
; CHECK-NEXT: [[TMP3:%.*]] = or i1 [[TMP1]], [[TMP2]]
; CHECK-NEXT: ret i1 [[TMP3]]
;
%1 = icmp ugt i32 %x, %y
%2 = icmp ne i32 %x, 0
%3 = or i1 %1, %2
ret i1 %3
}
define i1 @or_icmp3(i32 %x, i32 %y) {
; CHECK-LABEL: @or_icmp3(
; CHECK-NEXT: ret i1 true ; CHECK-NEXT: ret i1 true
; ;
%1 = icmp uge i32 %x, %y %1 = icmp uge i32 %x, %y
@ -403,8 +442,21 @@ define i1 @or_icmp2(i32 %x, i32 %y) {
ret i1 %3 ret i1 %3
} }
define i1 @or_icmp3(i32 %x, i32 %y) { define i1 @or_icmp4(i32 %x, i32 %y) {
; CHECK-LABEL: @or_icmp3( ; CHECK-LABEL: @or_icmp4(
; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i32 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[X]], 0
; CHECK-NEXT: [[TMP3:%.*]] = or i1 [[TMP1]], [[TMP2]]
; CHECK-NEXT: ret i1 [[TMP3]]
;
%1 = icmp ule i32 %x, %y
%2 = icmp ne i32 %x, 0
%3 = or i1 %1, %2
ret i1 %3
}
define i1 @or_icmp5(i32 %x, i32 %y) {
; CHECK-LABEL: @or_icmp5(
; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i32 [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i32 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[TMP1]] ; CHECK-NEXT: ret i1 [[TMP1]]
; ;
@ -414,6 +466,19 @@ define i1 @or_icmp3(i32 %x, i32 %y) {
ret i1 %3 ret i1 %3
} }
define i1 @or_icmp6(i32 %x, i32 %y) {
; CHECK-LABEL: @or_icmp6(
; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i32 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[X]], 0
; CHECK-NEXT: [[TMP3:%.*]] = or i1 [[TMP1]], [[TMP2]]
; CHECK-NEXT: ret i1 [[TMP3]]
;
%1 = icmp ule i32 %x, %y
%2 = icmp eq i32 %x, 0
%3 = or i1 %1, %2
ret i1 %3
}
; PR27869 - Look through casts to eliminate cmps and bitwise logic. ; PR27869 - Look through casts to eliminate cmps and bitwise logic.
define i32 @and_of_zexted_icmps(i32 %i) { define i32 @and_of_zexted_icmps(i32 %i) {