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Revert "[Hexagon] Check if operand is an immediate before getImm" 

This reverts r348787. The patch wasn't quite correct.

llvm-svn: 348792
This commit is contained in:
Krzysztof Parzyszek 2018-12-10 19:30:08 +00:00
parent 69f6098e89
commit c1b2d5905a
2 changed files with 12 additions and 55 deletions
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27
llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
View File

@ -502,8 +502,7 @@ bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp,
MIB.add(ImmOp); MIB.add(ImmOp);
OpStart = 4; OpStart = 4;
Changed = true; Changed = true;
} else if (HII->getAddrMode(*OldMI) == HexagonII::BaseImmOffset && } else if (HII->getAddrMode(*OldMI) == HexagonII::BaseImmOffset) {
OldMI->getOperand(2).isImm()) {
short NewOpCode = HII->changeAddrMode_io_abs(*OldMI); short NewOpCode = HII->changeAddrMode_io_abs(*OldMI);
assert(NewOpCode >= 0 && "Invalid New opcode\n"); assert(NewOpCode >= 0 && "Invalid New opcode\n");
MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)) MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode))
@ -519,19 +518,17 @@ bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp,
LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
} else if (ImmOpNum == 2) { } else if (ImmOpNum == 2 && OldMI->getOperand(3).getImm() == 0) {
if (OldMI->getOperand(3).isImm() && OldMI->getOperand(3).getImm() == 0) { short NewOpCode = HII->changeAddrMode_rr_io(*OldMI);
short NewOpCode = HII->changeAddrMode_rr_io(*OldMI); assert(NewOpCode >= 0 && "Invalid New opcode\n");
assert(NewOpCode >= 0 && "Invalid New opcode\n"); MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); MIB.add(OldMI->getOperand(0));
MIB.add(OldMI->getOperand(0)); MIB.add(OldMI->getOperand(1));
MIB.add(OldMI->getOperand(1)); MIB.add(ImmOp);
MIB.add(ImmOp); OpStart = 4;
OpStart = 4; Changed = true;
Changed = true; LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
}
} }
if (Changed) if (Changed)

40
llvm/test/CodeGen/Hexagon/addrmode-immop.mir
View File

@ -1,40 +0,0 @@
# RUN: llc -march=hexagon -run-pass amode-opt %s -o - | FileCheck %s
# REQUIRES: asserts
# Check that this doesn't crash.
# CHECK: $r2 = L2_loadri_io killed $r2, @f1 - 1
--- |
target triple = "hexagon-unknown-unknown-elf"
%s.0 = type { i32 (...)**, i32, i32, %s.1 }
%s.1 = type { i32, i32 }
@g0 = external dso_local unnamed_addr constant { [3 x i8*], [3 x i8*] }, align 4
; Function Attrs: norecurse
define void @f0() #0 {
b0:
%v0 = load i32 (%s.0*)*, i32 (%s.0*)** bitcast (i8* getelementptr (i8, i8* bitcast (i8** getelementptr inbounds ({ [3 x i8*], [3 x i8*] }, { [3 x i8*], [3 x i8*] }* @g0, i32 0, inrange i32 0, i32 3) to i8*), i32 sub (i32 ptrtoint (i32 (%s.0*)* @f1 to i32), i32 1)) to i32 (%s.0*)**), align 4
%v1 = call i32 %v0(%s.0* nonnull undef)
unreachable
}
; Function Attrs: norecurse nounwind
declare dso_local i32 @f1(%s.0*) #1 align 2
attributes #0 = { norecurse "target-cpu"="hexagonv60" }
attributes #1 = { norecurse nounwind "target-cpu"="hexagonv60" }
...
---
name: f0
tracksRegLiveness: true
body: |
bb.0.b0:
$r2 = A2_tfrsi @g0 + 12
$r2 = L2_loadri_io killed $r2, @f1 - 1 :: (load 4 from `i32 (%s.0*)** bitcast (i8* getelementptr (i8, i8* bitcast (i8** getelementptr inbounds ({ [3 x i8*], [3 x i8*] }, { [3 x i8*], [3 x i8*] }* @g0, i32 0, inrange i32 0, i32 3) to i8*), i32 sub (i32 ptrtoint (i32 (%s.0*)* @f1 to i32), i32 1)) to i32 (%s.0*)**)`)
ADJCALLSTACKDOWN 0, 0, implicit-def $r29, implicit-def dead $r30, implicit $r31, implicit $r30, implicit $r29
PS_callr_nr killed $r2, hexagoncsr, implicit undef $r0, implicit-def $r29, implicit-def dead $r0
ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit-def dead $r30, implicit-def dead $r31, implicit $r29
...