forked from OSchip/llvm-project
[PPCISelLowering] Avoid emitting calls to __multi3, __muloti4
After D108936, @llvm.smul.with.overflow.i64 was lowered to __multi3 instead of __mulodi4, which also doesn't exist on PowerPC 32-bit, not even with compiler-rt. Block it as well so that we get inline code. Because libgcc doesn't have __muloti4, we block that as well. Fixes #54460. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D122090
This commit is contained in:
Aaron Puchert
parent
bce1bf0ee2
commit
c1a31ee65b
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@ -1335,11 +1335,13 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
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}
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setLibcallName(RTLIB::MULO_I128, nullptr);
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if (!isPPC64) {
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// These libcalls are not available in 32-bit.
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setLibcallName(RTLIB::SHL_I128, nullptr);
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setLibcallName(RTLIB::SRL_I128, nullptr);
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setLibcallName(RTLIB::SRA_I128, nullptr);
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setLibcallName(RTLIB::MUL_I128, nullptr);
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setLibcallName(RTLIB::MULO_I64, nullptr);
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}
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@ -1,8 +1,10 @@
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; RUN: llc %s -mtriple=powerpc -o - | FileCheck %s
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; RUN: llc %s -mtriple=powerpc64 -o - | FileCheck %s
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define i1 @no__mulodi4(i32 %a, i64 %b, i32* %c) {
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; CHECK-LABEL: no__mulodi4
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; CHECK-NOT: bl __mulodi4
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; CHECK-NOT: bl __multi3
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entry:
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%0 = sext i32 %a to i64
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%1 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %0, i64 %b)
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@ -16,4 +18,14 @@ entry:
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ret i1 %7
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}
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define i1 @no__muloti4(i128 %a, i128 %b) {
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; CHECK-LABEL: no__muloti4
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; CHECK-NOT: bl __muloti4
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entry:
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%0 = call { i128, i1 } @llvm.smul.with.overflow.i128(i128 %a, i128 %b)
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%1 = extractvalue { i128, i1 } %0, 1
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ret i1 %1
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}
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declare { i64, i1 } @llvm.smul.with.overflow.i64(i64, i64)
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declare { i128, i1 } @llvm.smul.with.overflow.i128(i128, i128)
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@ -32,110 +32,103 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
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;
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; PPC32-LABEL: muloti_test:
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; PPC32: # %bb.0: # %start
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; PPC32-NEXT: mflr 0
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; PPC32-NEXT: stw 0, 4(1)
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; PPC32-NEXT: stwu 1, -64(1)
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; PPC32-NEXT: stw 24, 32(1) # 4-byte Folded Spill
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; PPC32-NEXT: mfcr 12
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; PPC32-NEXT: stw 26, 40(1) # 4-byte Folded Spill
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; PPC32-NEXT: mr 26, 7
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; PPC32-NEXT: stw 28, 48(1) # 4-byte Folded Spill
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; PPC32-NEXT: mr 28, 4
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; PPC32-NEXT: stw 29, 52(1) # 4-byte Folded Spill
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; PPC32-NEXT: mr 29, 8
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; PPC32-NEXT: mr 24, 3
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; PPC32-NEXT: li 3, 0
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; PPC32-NEXT: li 4, 0
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; PPC32-NEXT: li 7, 0
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; PPC32-NEXT: li 8, 0
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; PPC32-NEXT: stw 23, 28(1) # 4-byte Folded Spill
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; PPC32-NEXT: mr 23, 5
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; PPC32-NEXT: stw 25, 36(1) # 4-byte Folded Spill
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; PPC32-NEXT: mr 25, 9
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; PPC32-NEXT: stw 27, 44(1) # 4-byte Folded Spill
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; PPC32-NEXT: mr 27, 6
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; PPC32-NEXT: stw 30, 56(1) # 4-byte Folded Spill
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; PPC32-NEXT: mr 30, 10
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; PPC32-NEXT: stw 12, 24(1)
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; PPC32-NEXT: bl __multi3
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; PPC32-NEXT: mulhwu. 9, 26, 27
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; PPC32-NEXT: mfcr 9 # cr0
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; PPC32-NEXT: cmpwi 2, 26, 0
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; PPC32-NEXT: stw 9, 20(1)
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; PPC32-NEXT: cmpwi 3, 23, 0
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; PPC32-NEXT: crnor 12, 14, 10
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; PPC32-NEXT: cmpwi 4, 24, 0
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; PPC32-NEXT: mulhwu. 9, 23, 29
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; PPC32-NEXT: mulhwu. 26, 7, 6
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; PPC32-NEXT: mcrf 1, 0
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; PPC32-NEXT: mfcr 12
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; PPC32-NEXT: cmpwi 7, 5, 0
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; PPC32-NEXT: cmpwi 2, 7, 0
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; PPC32-NEXT: stw 22, 24(1) # 4-byte Folded Spill
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; PPC32-NEXT: mulhwu. 26, 5, 8
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; PPC32-NEXT: mcrf 5, 0
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; PPC32-NEXT: cmpwi 1, 25, 0
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; PPC32-NEXT: crnor 4, 6, 18
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; PPC32-NEXT: mulhwu. 9, 24, 30
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; PPC32-NEXT: stw 23, 28(1) # 4-byte Folded Spill
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; PPC32-NEXT: crnor 28, 30, 10
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; PPC32-NEXT: stw 29, 52(1) # 4-byte Folded Spill
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; PPC32-NEXT: cmpwi 2, 9, 0
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; PPC32-NEXT: mulhwu. 26, 3, 10
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; PPC32-NEXT: mcrf 6, 0
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; PPC32-NEXT: mulhwu. 0, 25, 28
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; PPC32-NEXT: mcrf 7, 0
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; PPC32-NEXT: or. 0, 28, 24
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; PPC32-NEXT: mcrf 2, 0
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; PPC32-NEXT: or. 0, 29, 26
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; PPC32-NEXT: crnor 5, 2, 10
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; PPC32-NEXT: mullw 10, 26, 27
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; PPC32-NEXT: lwz 26, 20(1)
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; PPC32-NEXT: mullw 9, 23, 29
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; PPC32-NEXT: add 9, 10, 9
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; PPC32-NEXT: mtcrf 128, 26 # cr0
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; PPC32-NEXT: crorc 6, 12, 2
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; PPC32-NEXT: crorc 20, 6, 22
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; PPC32-NEXT: mulhwu 7, 29, 27
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; PPC32-NEXT: add 9, 7, 9
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; PPC32-NEXT: cmplw 9, 7
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; PPC32-NEXT: crorc 21, 4, 26
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; PPC32-NEXT: cror 20, 20, 0
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; PPC32-NEXT: crorc 21, 21, 30
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; PPC32-NEXT: mullw 11, 25, 28
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; PPC32-NEXT: mullw 12, 24, 30
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; PPC32-NEXT: add 10, 12, 11
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; PPC32-NEXT: lwz 12, 24(1)
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; PPC32-NEXT: lwz 26, 40(1) # 4-byte Folded Reload
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; PPC32-NEXT: mulhwu 8, 28, 30
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; PPC32-NEXT: add 10, 8, 10
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; PPC32-NEXT: cmplw 10, 8
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; PPC32-NEXT: cror 21, 21, 0
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; PPC32-NEXT: cror 21, 5, 21
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; PPC32-NEXT: cmpwi 3, 3, 0
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; PPC32-NEXT: stw 24, 32(1) # 4-byte Folded Spill
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; PPC32-NEXT: crnor 29, 10, 14
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; PPC32-NEXT: stw 25, 36(1) # 4-byte Folded Spill
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; PPC32-NEXT: mulhwu. 26, 9, 4
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; PPC32-NEXT: stw 27, 44(1) # 4-byte Folded Spill
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; PPC32-NEXT: crorc 28, 28, 6
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; PPC32-NEXT: stw 28, 48(1) # 4-byte Folded Spill
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; PPC32-NEXT: crorc 20, 28, 22
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; PPC32-NEXT: stw 30, 56(1) # 4-byte Folded Spill
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; PPC32-NEXT: mulhwu 0, 6, 10
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; PPC32-NEXT: stw 12, 20(1)
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; PPC32-NEXT: crorc 21, 29, 26
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; PPC32-NEXT: crorc 21, 21, 2
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; PPC32-NEXT: li 11, 0
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; PPC32-NEXT: mullw 26, 5, 10
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; PPC32-NEXT: addc 0, 26, 0
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; PPC32-NEXT: mulhwu 29, 5, 10
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; PPC32-NEXT: addze 29, 29
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; PPC32-NEXT: mullw 23, 5, 8
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; PPC32-NEXT: mullw 22, 7, 6
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; PPC32-NEXT: mulhwu 30, 6, 9
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; PPC32-NEXT: mulhwu 12, 5, 9
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; PPC32-NEXT: mulhwu 28, 8, 6
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; PPC32-NEXT: mullw 25, 6, 9
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; PPC32-NEXT: mullw 24, 5, 9
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; PPC32-NEXT: mullw 5, 9, 4
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; PPC32-NEXT: add 9, 22, 23
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; PPC32-NEXT: add 9, 28, 9
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; PPC32-NEXT: cmplw 1, 9, 28
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; PPC32-NEXT: cror 20, 20, 4
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; PPC32-NEXT: mullw 23, 3, 10
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; PPC32-NEXT: add 26, 23, 5
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; PPC32-NEXT: addc 5, 25, 0
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; PPC32-NEXT: addze 30, 30
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; PPC32-NEXT: or. 3, 4, 3
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; PPC32-NEXT: mulhwu 27, 4, 10
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; PPC32-NEXT: mcrf 1, 0
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; PPC32-NEXT: addc 3, 29, 30
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; PPC32-NEXT: add 26, 27, 26
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; PPC32-NEXT: cmplw 6, 26, 27
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; PPC32-NEXT: cror 21, 21, 24
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; PPC32-NEXT: mullw 0, 4, 10
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; PPC32-NEXT: or. 4, 8, 7
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; PPC32-NEXT: addze 4, 11
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; PPC32-NEXT: addc 7, 24, 3
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; PPC32-NEXT: crnor 22, 2, 6
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; PPC32-NEXT: mullw 28, 8, 6
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; PPC32-NEXT: adde 8, 12, 4
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; PPC32-NEXT: addc 3, 0, 28
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; PPC32-NEXT: adde 9, 26, 9
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; PPC32-NEXT: addc 4, 7, 3
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; PPC32-NEXT: adde 3, 8, 9
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; PPC32-NEXT: cror 21, 22, 21
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; PPC32-NEXT: cmplw 4, 7
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; PPC32-NEXT: cmplw 1, 3, 8
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; PPC32-NEXT: lwz 12, 20(1)
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; PPC32-NEXT: cror 20, 21, 20
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; PPC32-NEXT: mullw 0, 29, 27
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; PPC32-NEXT: crandc 21, 4, 6
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; PPC32-NEXT: crand 22, 6, 0
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; PPC32-NEXT: cror 21, 22, 21
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; PPC32-NEXT: crnor 20, 20, 21
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; PPC32-NEXT: li 7, 1
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; PPC32-NEXT: mullw 6, 6, 10
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; PPC32-NEXT: bc 12, 20, .LBB0_1
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; PPC32-NEXT: b .LBB0_2
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; PPC32-NEXT: .LBB0_1: # %start
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; PPC32-NEXT: li 7, 0
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; PPC32-NEXT: .LBB0_2: # %start
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; PPC32-NEXT: mtcrf 32, 12 # cr2
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; PPC32-NEXT: mtcrf 16, 12 # cr3
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; PPC32-NEXT: mtcrf 8, 12 # cr4
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; PPC32-NEXT: lwz 29, 52(1) # 4-byte Folded Reload
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; PPC32-NEXT: mullw 7, 28, 30
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; PPC32-NEXT: addc 7, 7, 0
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; PPC32-NEXT: adde 11, 10, 9
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; PPC32-NEXT: addc 9, 4, 7
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; PPC32-NEXT: adde 8, 3, 11
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; PPC32-NEXT: cmplw 6, 9, 4
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; PPC32-NEXT: cmplw 8, 3
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; PPC32-NEXT: crand 22, 2, 24
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; PPC32-NEXT: crandc 23, 0, 2
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; PPC32-NEXT: cror 22, 22, 23
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; PPC32-NEXT: crnor 20, 20, 22
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; PPC32-NEXT: li 3, 1
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; PPC32-NEXT: bc 12, 20, .LBB0_2
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; PPC32-NEXT: # %bb.1: # %start
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; PPC32-NEXT: ori 7, 3, 0
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; PPC32-NEXT: b .LBB0_3
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; PPC32-NEXT: .LBB0_2: # %start
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; PPC32-NEXT: li 7, 0
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; PPC32-NEXT: .LBB0_3: # %start
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; PPC32-NEXT: mr 3, 8
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; PPC32-NEXT: mr 4, 9
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; PPC32-NEXT: lwz 30, 56(1) # 4-byte Folded Reload
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; PPC32-NEXT: lwz 29, 52(1) # 4-byte Folded Reload
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; PPC32-NEXT: lwz 28, 48(1) # 4-byte Folded Reload
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; PPC32-NEXT: lwz 27, 44(1) # 4-byte Folded Reload
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; PPC32-NEXT: lwz 26, 40(1) # 4-byte Folded Reload
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; PPC32-NEXT: lwz 25, 36(1) # 4-byte Folded Reload
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; PPC32-NEXT: lwz 24, 32(1) # 4-byte Folded Reload
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; PPC32-NEXT: lwz 23, 28(1) # 4-byte Folded Reload
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; PPC32-NEXT: lwz 0, 68(1)
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; PPC32-NEXT: lwz 22, 24(1) # 4-byte Folded Reload
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; PPC32-NEXT: addi 1, 1, 64
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; PPC32-NEXT: mtlr 0
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; PPC32-NEXT: blr
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start:
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%0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2
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@ -208,43 +208,46 @@ define <3 x i1> @test_urem_vec(<3 x i11> %X) nounwind {
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define i1 @test_urem_oversized(i66 %X) nounwind {
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; PPC-LABEL: test_urem_oversized:
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; PPC: # %bb.0:
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; PPC-NEXT: mflr 0
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; PPC-NEXT: stw 0, 4(1)
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; PPC-NEXT: stwu 1, -16(1)
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; PPC-NEXT: mr 6, 5
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; PPC-NEXT: mr 5, 4
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; PPC-NEXT: mr 4, 3
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; PPC-NEXT: lis 3, 12057
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; PPC-NEXT: lis 7, -12795
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; PPC-NEXT: ori 9, 3, 37186
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; PPC-NEXT: ori 10, 7, 40665
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; PPC-NEXT: li 3, 0
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; PPC-NEXT: li 7, 0
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; PPC-NEXT: li 8, 2
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; PPC-NEXT: bl __multi3
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; PPC-NEXT: rotlwi 7, 6, 31
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; PPC-NEXT: lis 3, -5526
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; PPC-NEXT: rlwimi 7, 5, 31, 0, 0
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; PPC-NEXT: rotlwi 5, 5, 31
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; PPC-NEXT: rlwimi 5, 4, 31, 0, 0
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; PPC-NEXT: ori 3, 3, 61135
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; PPC-NEXT: cmplwi 1, 5, 13
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; PPC-NEXT: cmplw 7, 3
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; PPC-NEXT: rlwinm 4, 4, 31, 31, 31
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; PPC-NEXT: lis 6, -12795
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; PPC-NEXT: ori 6, 6, 40665
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; PPC-NEXT: mulhwu 7, 5, 6
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; PPC-NEXT: lis 8, 12057
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; PPC-NEXT: ori 8, 8, 37186
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; PPC-NEXT: mullw 10, 4, 6
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; PPC-NEXT: addc 7, 10, 7
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; PPC-NEXT: mullw 3, 3, 6
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; PPC-NEXT: mullw 11, 5, 6
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; PPC-NEXT: mulhwu 6, 4, 6
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; PPC-NEXT: addze 6, 6
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; PPC-NEXT: slwi 4, 4, 1
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; PPC-NEXT: mulhwu 9, 5, 8
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; PPC-NEXT: mullw 8, 5, 8
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; PPC-NEXT: addc 7, 8, 7
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; PPC-NEXT: addze 9, 9
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; PPC-NEXT: slwi 5, 5, 1
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; PPC-NEXT: add 6, 6, 9
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; PPC-NEXT: add 3, 5, 3
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; PPC-NEXT: rotlwi 8, 11, 31
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; PPC-NEXT: sub 4, 6, 4
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; PPC-NEXT: lis 5, -5526
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; PPC-NEXT: rlwimi 8, 7, 31, 0, 0
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; PPC-NEXT: rotlwi 7, 7, 31
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; PPC-NEXT: add 3, 4, 3
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; PPC-NEXT: ori 5, 5, 61135
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; PPC-NEXT: rlwimi 7, 3, 31, 0, 0
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; PPC-NEXT: cmplw 8, 5
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; PPC-NEXT: cmplwi 1, 7, 13
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; PPC-NEXT: rlwinm 3, 3, 31, 31, 31
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; PPC-NEXT: crand 20, 6, 0
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; PPC-NEXT: crandc 21, 4, 6
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; PPC-NEXT: rlwimi. 4, 6, 1, 30, 30
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; PPC-NEXT: rlwimi. 3, 11, 1, 30, 30
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; PPC-NEXT: cror 20, 20, 21
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; PPC-NEXT: crnand 20, 2, 20
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; PPC-NEXT: li 3, 1
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; PPC-NEXT: bc 12, 20, .LBB5_1
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; PPC-NEXT: b .LBB5_2
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; PPC-NEXT: blr
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; PPC-NEXT: .LBB5_1:
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; PPC-NEXT: li 3, 0
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; PPC-NEXT: .LBB5_2:
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; PPC-NEXT: lwz 0, 20(1)
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; PPC-NEXT: addi 1, 1, 16
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; PPC-NEXT: mtlr 0
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; PPC-NEXT: blr
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;
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; PPC64LE-LABEL: test_urem_oversized:
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