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Some 32-bit arm corefiles on darwin may have their general purpose 

register set indicated by ARM_THREAD_STATE32 (value 9) instead of
the old ARM_THREAD_STATE (value 1); this patch changes lldb to
accept either register set flavor code.

<rdar://problem/24246257>

llvm-svn: 258289
This commit is contained in:
Jason Molenda 2016-01-20 05:17:13 +00:00
parent 3c43dc27ab
commit c197e81d07
3 changed files with 9 additions and 5 deletions
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3
lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
View File

@ -541,6 +541,7 @@ public:
lldb::offset_t next_thread_state = offset + (count * 4);
switch (flavor)
{
case GPRAltRegSet:
case GPRRegSet:
for (uint32_t i=0; i<count; ++i)
{
@ -5059,7 +5060,7 @@ ObjectFileMachO::GetEntryPointAddress ()
switch (m_header.cputype)
{
case llvm::MachO::CPU_TYPE_ARM:
if (flavor == 1) // ARM_THREAD_STATE from mach/arm/thread_status.h
if (flavor == 1 || flavor == 9) // ARM_THREAD_STATE/ARM_THREAD_STATE32 from mach/arm/thread_status.h
{
offset += 60; // This is the offset of pc in the GPR thread state data structure.
start_address = m_data.GetU32(&offset);

2
lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm.cpp
View File

@ -596,6 +596,7 @@ RegisterContextDarwin_arm::ReadRegisterSet (uint32_t set, bool force)
switch (set)
{
case GPRRegSet: return ReadGPR(force);
case GPRAltRegSet: return ReadGPR(force);
case FPURegSet: return ReadFPU(force);
case EXCRegSet: return ReadEXC(force);
case DBGRegSet: return ReadDBG(force);
@ -613,6 +614,7 @@ RegisterContextDarwin_arm::WriteRegisterSet (uint32_t set)
switch (set)
{
case GPRRegSet: return WriteGPR();
case GPRAltRegSet: return WriteGPR();
case FPURegSet: return WriteFPU();
case EXCRegSet: return WriteEXC();
case DBGRegSet: return WriteDBG();

9
lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm.h
View File

@ -162,10 +162,11 @@ public:
protected:
enum
{
GPRRegSet = 1, // ARM_THREAD_STATE
FPURegSet = 2, // ARM_VFP_STATE
EXCRegSet = 3, // ARM_EXCEPTION_STATE
DBGRegSet = 4 // ARM_DEBUG_STATE
GPRRegSet = 1, // ARM_THREAD_STATE
GPRAltRegSet = 9, // ARM_THREAD_STATE32
FPURegSet = 2, // ARM_VFP_STATE
EXCRegSet = 3, // ARM_EXCEPTION_STATE
DBGRegSet = 4 // ARM_DEBUG_STATE
};
enum