From c18e90369d313932cb50446baf38c2f85ed72e40 Mon Sep 17 00:00:00 2001
From: Anton Korobeynikov <anton@korobeynikov.info>
Date: Wed, 9 Jan 2019 13:03:01 +0000
Subject: [PATCH] [MSP430] Optimize 'shl x, 8[+ N] -> swpb(zext(x)) [<< N]' for
 i16

Perform additional simplification to reduce shift amount.

Patch by Kristina Bessonova!

Differential Revision: https://reviews.llvm.org/D56016

llvm-svn: 350712
---
 llvm/lib/Target/MSP430/MSP430ISelLowering.cpp | 25 +++++++++++++------
 llvm/test/CodeGen/MSP430/shifts.ll            | 11 ++++++++
 2 files changed, 29 insertions(+), 7 deletions(-)

diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
index 3df1f7b9a783..3e706134afc5 100644
--- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
+++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
@@ -954,15 +954,26 @@ SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
   // Expand the stuff into sequence of shifts.
   SDValue Victim = N->getOperand(0);
 
-  if ((Opc == ISD::SRA || Opc == ISD::SRL) && ShiftAmount >= 8) {
-    // foo >> (8 + N) => sxt(swpb(foo)) >> N
+  if (ShiftAmount >= 8) {
     assert(VT == MVT::i16 && "Can not shift i8 by 8 and more");
-    Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim);
-    if (Opc == ISD::SRA)
-      Victim = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, Victim,
-                           DAG.getValueType(MVT::i8));
-    else
+    switch(Opc) {
+    default:
+      llvm_unreachable("Unknown shift");
+    case ISD::SHL:
+      // foo << (8 + N) => swpb(zext(foo)) << N
       Victim = DAG.getZeroExtendInReg(Victim, dl, MVT::i8);
+      Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim);
+      break;
+    case ISD::SRA:
+    case ISD::SRL:
+      // foo >> (8 + N) => sxt(swpb(foo)) >> N
+      Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim);
+      Victim = (Opc == ISD::SRA)
+                   ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, Victim,
+                                 DAG.getValueType(MVT::i8))
+                   : DAG.getZeroExtendInReg(Victim, dl, MVT::i8);
+      break;
+    }
     ShiftAmount -= 8;
   }
 
diff --git a/llvm/test/CodeGen/MSP430/shifts.ll b/llvm/test/CodeGen/MSP430/shifts.ll
index 073251943d01..5a1fc9c324bb 100644
--- a/llvm/test/CodeGen/MSP430/shifts.ll
+++ b/llvm/test/CodeGen/MSP430/shifts.ll
@@ -74,3 +74,14 @@ entry:
   %shr = lshr i16 %a, 10
   ret i16 %shr
 }
+
+define i16 @lshl10_i16(i16 %a) #0 {
+entry:
+; CHECK-LABEL: lshl10_i16:
+; CHECK:      mov.b r12, r12
+; CHECK-NEXT: swpb r12
+; CHECK-NEXT: add r12, r12
+; CHECK-NEXT: add r12, r12
+  %shl = shl i16 %a, 10
+  ret i16 %shl
+}