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bfi A, (and B, C1), C2) -> bfi A, B, C2 iff C1 & C2 == C1. rdar://8458663 

llvm-svn: 121746
This commit is contained in:
Evan Cheng 2010-12-14 03:22:07 +00:00
parent 8b2fe6dcbd
commit c177813755
2 changed files with 33 additions and 0 deletions
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20
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -4809,6 +4809,25 @@ static SDValue PerformORCombine(SDNode *N,
return SDValue(); return SDValue();
} }
/// PerformBFICombine - (bfi A, (and B, C1), C2) -> (bfi A, B, C2) iff
/// C1 & C2 == C1.
static SDValue PerformBFICombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI) {
SDValue N1 = N->getOperand(1);
if (N1.getOpcode() == ISD::AND) {
ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
if (!N11C)
return SDValue();
unsigned Mask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
unsigned Mask2 = N11C->getZExtValue();
if ((Mask & Mask2) == Mask2)
return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0),
N->getOperand(0), N1.getOperand(0),
N->getOperand(2));
}
return SDValue();
}
/// PerformVMOVRRDCombine - Target-specific dag combine xforms for /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
/// ARMISD::VMOVRRD. /// ARMISD::VMOVRRD.
static SDValue PerformVMOVRRDCombine(SDNode *N, static SDValue PerformVMOVRRDCombine(SDNode *N,
@ -5398,6 +5417,7 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget); case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
case ISD::OR: return PerformORCombine(N, DCI, Subtarget); case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
case ISD::AND: return PerformANDCombine(N, DCI); case ISD::AND: return PerformANDCombine(N, DCI);
case ARMISD::BFI: return PerformBFICombine(N, DCI);
case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI); case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG); case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG); case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG);

13
llvm/test/CodeGen/ARM/bfi.ll
View File

@ -49,3 +49,16 @@ define i32 @f4(i32 %a) nounwind {
%ins12 = or i32 %ins7, 3137 %ins12 = or i32 %ins7, 3137
ret i32 %ins12 ret i32 %ins12
} }
; rdar://8458663
define i32 @f5(i32 %a, i32 %b) nounwind {
entry:
; CHECK: f5:
; CHECK-NOT: bfc
; CHECK: bfi r0, r1, #20, #4
%0 = and i32 %a, -15728641
%1 = shl i32 %b, 20
%2 = and i32 %1, 15728640
%3 = or i32 %2, %0
ret i32 %3
}