forked from OSchip/llvm-project
[X86][SSE] Add tests for trunc(usubsat()) patterns.
This commit is contained in:
Simon Pilgrim
parent
3b7580951c
commit
c1664c5a27
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@ -1,15 +1,16 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE,SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=CHECK,SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE42
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX,AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefixes=CHECK,AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
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declare i32 @llvm.usub.sat.i32 (i32, i32)
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declare i32 @llvm.usub.sat.i32 (i32, i32)
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declare i64 @llvm.usub.sat.i64 (i64, i64)
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declare i64 @llvm.usub.sat.i64 (i64, i64)
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declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16>, <8 x i16>)
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declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16>, <8 x i16>)
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declare <8 x i32> @llvm.usub.sat.v8i32(<8 x i32>, <8 x i32>)
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; fold (usub_sat x, undef) -> 0
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; fold (usub_sat x, undef) -> 0
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define i32 @combine_undef_i32(i32 %a0) {
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define i32 @combine_undef_i32(i32 %a0) {
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@ -114,3 +115,153 @@ define <8 x i16> @combine_self_v8i16(<8 x i16> %a0) {
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%1 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %a0, <8 x i16> %a0)
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%1 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %a0, <8 x i16> %a0)
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ret <8 x i16> %1
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ret <8 x i16> %1
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}
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}
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; FIXME: fold (trunc (usub_sat zext(x), y)) -> usub_sat(x, trunc(umin(y,satlimit)))
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define i16 @combine_trunc_i32_i16(i16 %a0, i32 %a1) {
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; CHECK-LABEL: combine_trunc_i32_i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzwl %di, %eax
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: subl %esi, %eax
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; CHECK-NEXT: cmovbl %ecx, %eax
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; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
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; CHECK-NEXT: retq
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%1 = zext i16 %a0 to i32
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%2 = call i32 @llvm.usub.sat.i32(i32 %1, i32 %a1)
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%3 = trunc i32 %2 to i16
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ret i16 %3
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}
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define <8 x i8> @combine_trunc_v8i16_v8i8(<8 x i8> %a0, <8 x i16> %a1) {
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; SSE2-LABEL: combine_trunc_v8i16_v8i8:
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; SSE2: # %bb.0:
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; SSE2-NEXT: pxor %xmm2, %xmm2
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; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
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; SSE2-NEXT: psubusw %xmm1, %xmm0
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; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE2-NEXT: packuswb %xmm0, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: combine_trunc_v8i16_v8i8:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
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; SSE41-NEXT: psubusw %xmm1, %xmm0
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; SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
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; SSE41-NEXT: retq
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;
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; SSE42-LABEL: combine_trunc_v8i16_v8i8:
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; SSE42: # %bb.0:
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; SSE42-NEXT: pmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
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; SSE42-NEXT: psubusw %xmm1, %xmm0
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; SSE42-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
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; SSE42-NEXT: retq
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;
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; AVX-LABEL: combine_trunc_v8i16_v8i8:
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; AVX: # %bb.0:
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; AVX-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
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; AVX-NEXT: vpsubusw %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
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; AVX-NEXT: retq
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%1 = zext <8 x i8> %a0 to <8 x i16>
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%2 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %1, <8 x i16> %a1)
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%3 = trunc <8 x i16> %2 to <8 x i8>
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ret <8 x i8> %3
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}
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define <8 x i16> @combine_trunc_v8i32_v8i16(<8 x i16> %a0, <8 x i32> %a1) {
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; SSE2-LABEL: combine_trunc_v8i32_v8i16:
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; SSE2: # %bb.0:
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; SSE2-NEXT: pxor %xmm4, %xmm4
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; SSE2-NEXT: movdqa %xmm0, %xmm3
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; SSE2-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm4[4],xmm3[5],xmm4[5],xmm3[6],xmm4[6],xmm3[7],xmm4[7]
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3]
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; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648]
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; SSE2-NEXT: movdqa %xmm0, %xmm5
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; SSE2-NEXT: psubd %xmm1, %xmm0
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; SSE2-NEXT: pxor %xmm4, %xmm1
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; SSE2-NEXT: por %xmm4, %xmm5
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; SSE2-NEXT: pcmpgtd %xmm1, %xmm5
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; SSE2-NEXT: pand %xmm5, %xmm0
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; SSE2-NEXT: movdqa %xmm2, %xmm1
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; SSE2-NEXT: pxor %xmm4, %xmm1
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; SSE2-NEXT: por %xmm3, %xmm4
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; SSE2-NEXT: pcmpgtd %xmm1, %xmm4
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; SSE2-NEXT: psubd %xmm2, %xmm3
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; SSE2-NEXT: pand %xmm4, %xmm3
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; SSE2-NEXT: pslld $16, %xmm3
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; SSE2-NEXT: psrad $16, %xmm3
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; SSE2-NEXT: pslld $16, %xmm0
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; SSE2-NEXT: psrad $16, %xmm0
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; SSE2-NEXT: packssdw %xmm3, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: combine_trunc_v8i32_v8i16:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pxor %xmm4, %xmm4
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; SSE41-NEXT: pmovzxwd {{.*#+}} xmm3 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
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; SSE41-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7]
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; SSE41-NEXT: pmaxud %xmm1, %xmm3
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; SSE41-NEXT: psubd %xmm1, %xmm3
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; SSE41-NEXT: pmaxud %xmm2, %xmm0
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; SSE41-NEXT: psubd %xmm2, %xmm0
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; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm4[1],xmm0[2],xmm4[3],xmm0[4],xmm4[5],xmm0[6],xmm4[7]
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; SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0],xmm4[1],xmm3[2],xmm4[3],xmm3[4],xmm4[5],xmm3[6],xmm4[7]
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; SSE41-NEXT: packusdw %xmm0, %xmm3
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; SSE41-NEXT: movdqa %xmm3, %xmm0
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; SSE41-NEXT: retq
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;
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; SSE42-LABEL: combine_trunc_v8i32_v8i16:
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; SSE42: # %bb.0:
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; SSE42-NEXT: pxor %xmm4, %xmm4
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; SSE42-NEXT: pmovzxwd {{.*#+}} xmm3 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
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; SSE42-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7]
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; SSE42-NEXT: pmaxud %xmm1, %xmm3
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; SSE42-NEXT: psubd %xmm1, %xmm3
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; SSE42-NEXT: pmaxud %xmm2, %xmm0
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; SSE42-NEXT: psubd %xmm2, %xmm0
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; SSE42-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm4[1],xmm0[2],xmm4[3],xmm0[4],xmm4[5],xmm0[6],xmm4[7]
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; SSE42-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0],xmm4[1],xmm3[2],xmm4[3],xmm3[4],xmm4[5],xmm3[6],xmm4[7]
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; SSE42-NEXT: packusdw %xmm0, %xmm3
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; SSE42-NEXT: movdqa %xmm3, %xmm0
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; SSE42-NEXT: retq
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;
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; AVX1-LABEL: combine_trunc_v8i32_v8i16:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
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; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
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; AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
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; AVX1-NEXT: vpmaxud %xmm1, %xmm2, %xmm2
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; AVX1-NEXT: vpsubd %xmm1, %xmm2, %xmm1
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; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = <0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u>
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; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
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; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
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; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; AVX1-NEXT: vzeroupper
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_trunc_v8i32_v8i16:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
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; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: vpsubd %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u,16,17,20,21,24,25,28,29,u,u,u,u,u,u,u,u]
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; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
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; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
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; AVX2-NEXT: vzeroupper
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: combine_trunc_v8i32_v8i16:
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; AVX512: # %bb.0:
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; AVX512-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
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; AVX512-NEXT: vpmovusdw %zmm1, %ymm1
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; AVX512-NEXT: vpsubusw %xmm1, %xmm0, %xmm0
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; AVX512-NEXT: vzeroupper
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; AVX512-NEXT: retq
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%1 = zext <8 x i16> %a0 to <8 x i32>
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%2 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> %1, <8 x i32> %a1)
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%3 = trunc <8 x i32> %2 to <8 x i16>
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ret <8 x i16> %3
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}
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