forked from OSchip/llvm-project
[WebAssembly] SIMD encoding tests
Modifies existing SIMD tests to also check that SIMD instructions are lowered to the expected bytes. This CL depends on D50597. Reviewers: aheejin Subscribers: sunfish, jgravelle-google, sbc100, llvm-commits Differential Revision: https://reviews.llvm.org/D50660 Patch by Thomas Lively (tlively) llvm-svn: 339712
This commit is contained in:
Heejin Ahn
parent
73b7e9f65e
commit
c15a87848b
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@ -1,9 +1,9 @@
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128-VM
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-simd128 | FileCheck %s --check-prefixes CHECK,NO-SIMD128
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128
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; RUN: llc < %s -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128 --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128
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; RUN: llc < %s -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128 -fast-isel --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128
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; RUN: llc < %s -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128 --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128-VM
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; RUN: llc < %s -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128 -fast-isel --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128-VM
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; RUN: llc < %s -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-simd128 --show-mc-encoding | FileCheck %s --check-prefixes CHECK,NO-SIMD128
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; RUN: llc < %s -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-simd128 -fast-isel --show-mc-encoding | FileCheck %s --check-prefixes CHECK,NO-SIMD128
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; Test that basic SIMD128 arithmetic operations assemble as expected.
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@ -17,8 +17,8 @@ target triple = "wasm32-unknown-unknown"
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; NO-SIMD128-NOT: i8x16
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i8x16.add $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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; SIMD128: i8x16.add $push0=, $0, $1 # encoding: [0xfd,0x18]{{$}}
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; SIMD128: return $pop0 #
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define <16 x i8> @add_v16i8(<16 x i8> %x, <16 x i8> %y) {
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%a = add <16 x i8> %x, %y
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ret <16 x i8> %a
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@ -28,8 +28,8 @@ define <16 x i8> @add_v16i8(<16 x i8> %x, <16 x i8> %y) {
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; NO-SIMD128-NOT: i8x16
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i8x16.sub $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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; SIMD128: i8x16.sub $push0=, $0, $1 # encoding: [0xfd,0x1c]{{$}}
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; SIMD128: return $pop0 #
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define <16 x i8> @sub_v16i8(<16 x i8> %x, <16 x i8> %y) {
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%a = sub <16 x i8> %x, %y
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ret <16 x i8> %a
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@ -39,8 +39,8 @@ define <16 x i8> @sub_v16i8(<16 x i8> %x, <16 x i8> %y) {
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; NO-SIMD128-NOT: i8x16
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i8x16.mul $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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; SIMD128: i8x16.mul $push0=, $0, $1 # encoding: [0xfd,0x20]{{$}}
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; SIMD128: return $pop0 #
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define <16 x i8> @mul_v16i8(<16 x i8> %x, <16 x i8> %y) {
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%a = mul <16 x i8> %x, %y
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ret <16 x i8> %a
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@ -53,8 +53,8 @@ define <16 x i8> @mul_v16i8(<16 x i8> %x, <16 x i8> %y) {
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; NO-SIMD128-NOT: i16x8
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i16x8.add $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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; SIMD128: i16x8.add $push0=, $0, $1 # encoding: [0xfd,0x19]{{$}}
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; SIMD128: return $pop0 #
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define <8 x i16> @add_v8i16(<8 x i16> %x, <8 x i16> %y) {
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%a = add <8 x i16> %x, %y
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ret <8 x i16> %a
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@ -64,8 +64,8 @@ define <8 x i16> @add_v8i16(<8 x i16> %x, <8 x i16> %y) {
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; NO-SIMD128-NOT: i16x8
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i16x8.sub $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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; SIMD128: i16x8.sub $push0=, $0, $1 # encoding: [0xfd,0x1d]{{$}}
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; SIMD128: return $pop0 #
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define <8 x i16> @sub_v8i16(<8 x i16> %x, <8 x i16> %y) {
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%a = sub <8 x i16> %x, %y
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ret <8 x i16> %a
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@ -75,8 +75,8 @@ define <8 x i16> @sub_v8i16(<8 x i16> %x, <8 x i16> %y) {
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; NO-SIMD128-NOT: i16x8
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i16x8.mul $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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; SIMD128: i16x8.mul $push0=, $0, $1 # encoding: [0xfd,0x21]{{$}}
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; SIMD128: return $pop0 #
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define <8 x i16> @mul_v8i16(<8 x i16> %x, <8 x i16> %y) {
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%a = mul <8 x i16> %x, %y
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ret <8 x i16> %a
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@ -89,8 +89,8 @@ define <8 x i16> @mul_v8i16(<8 x i16> %x, <8 x i16> %y) {
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; NO-SIMD128-NOT: i32x4
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i32x4.add $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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; SIMD128: i32x4.add $push0=, $0, $1 # encoding: [0xfd,0x1a]{{$}}
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; SIMD128: return $pop0 #
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define <4 x i32> @add_v4i32(<4 x i32> %x, <4 x i32> %y) {
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%a = add <4 x i32> %x, %y
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ret <4 x i32> %a
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@ -100,8 +100,8 @@ define <4 x i32> @add_v4i32(<4 x i32> %x, <4 x i32> %y) {
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; NO-SIMD128-NOT: i32x4
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i32x4.sub $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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; SIMD128: i32x4.sub $push0=, $0, $1 # encoding: [0xfd,0x1e]{{$}}
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; SIMD128: return $pop0 #
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define <4 x i32> @sub_v4i32(<4 x i32> %x, <4 x i32> %y) {
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%a = sub <4 x i32> %x, %y
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ret <4 x i32> %a
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@ -111,8 +111,8 @@ define <4 x i32> @sub_v4i32(<4 x i32> %x, <4 x i32> %y) {
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; NO-SIMD128-NOT: i32x4
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i32x4.mul $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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; SIMD128: i32x4.mul $push0=, $0, $1 # encoding: [0xfd,0x22]{{$}}
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; SIMD128: return $pop0 #
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define <4 x i32> @mul_v4i32(<4 x i32> %x, <4 x i32> %y) {
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%a = mul <4 x i32> %x, %y
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ret <4 x i32> %a
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@ -126,8 +126,8 @@ define <4 x i32> @mul_v4i32(<4 x i32> %x, <4 x i32> %y) {
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; SIMD128-VM-NOT: i64x2
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i64x2.add $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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; SIMD128: i64x2.add $push0=, $0, $1 # encoding: [0xfd,0x1b]{{$}}
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; SIMD128: return $pop0 #
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define <2 x i64> @add_v2i64(<2 x i64> %x, <2 x i64> %y) {
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%a = add <2 x i64> %x, %y
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ret <2 x i64> %a
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@ -138,8 +138,8 @@ define <2 x i64> @add_v2i64(<2 x i64> %x, <2 x i64> %y) {
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; SIMD128-VM-NOT: i64x2
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i64x2.sub $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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; SIMD128: i64x2.sub $push0=, $0, $1 # encoding: [0xfd,0x1f]{{$}}
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; SIMD128: return $pop0 #
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define <2 x i64> @sub_v2i64(<2 x i64> %x, <2 x i64> %y) {
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%a = sub <2 x i64> %x, %y
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ret <2 x i64> %a
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@ -150,8 +150,8 @@ define <2 x i64> @sub_v2i64(<2 x i64> %x, <2 x i64> %y) {
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; SIMD128-VM-NOT: i64x2
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i64x2.mul $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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; SIMD128: i64x2.mul $push0=, $0, $1 # encoding: [0xfd,0x23]{{$}}
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; SIMD128: return $pop0 #
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define <2 x i64> @mul_v2i64(<2 x i64> %x, <2 x i64> %y) {
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%a = mul <2 x i64> %x, %y
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ret <2 x i64> %a
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@ -164,8 +164,8 @@ define <2 x i64> @mul_v2i64(<2 x i64> %x, <2 x i64> %y) {
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; NO-SIMD128-NOT: f32x4
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: f32x4.add $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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; SIMD128: f32x4.add $push0=, $0, $1 # encoding: [0xfd,0x7a]{{$}}
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; SIMD128: return $pop0 #
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define <4 x float> @add_v4f32(<4 x float> %x, <4 x float> %y) {
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%a = fadd <4 x float> %x, %y
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ret <4 x float> %a
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@ -175,8 +175,8 @@ define <4 x float> @add_v4f32(<4 x float> %x, <4 x float> %y) {
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; NO-SIMD128-NOT: f32x4
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: f32x4.sub $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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; SIMD128: f32x4.sub $push0=, $0, $1 # encoding: [0xfd,0x7c]{{$}}
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; SIMD128: return $pop0 #
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define <4 x float> @sub_v4f32(<4 x float> %x, <4 x float> %y) {
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%a = fsub <4 x float> %x, %y
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ret <4 x float> %a
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@ -186,8 +186,8 @@ define <4 x float> @sub_v4f32(<4 x float> %x, <4 x float> %y) {
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; NO-SIMD128-NOT: f32x4
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: f32x4.div $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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; SIMD128: f32x4.div $push0=, $0, $1 # encoding: [0xfd,0x7e]{{$}}
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; SIMD128: return $pop0 #
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define <4 x float> @div_v4f32(<4 x float> %x, <4 x float> %y) {
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%a = fdiv <4 x float> %x, %y
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ret <4 x float> %a
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@ -197,8 +197,8 @@ define <4 x float> @div_v4f32(<4 x float> %x, <4 x float> %y) {
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; NO-SIMD128-NOT: f32x4
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: f32x4.mul $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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; SIMD128: f32x4.mul $push0=, $0, $1 # encoding: [0xfd,0x80]{{$}}
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; SIMD128: return $pop0 #
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define <4 x float> @mul_v4f32(<4 x float> %x, <4 x float> %y) {
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%a = fmul <4 x float> %x, %y
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ret <4 x float> %a
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@ -212,8 +212,8 @@ define <4 x float> @mul_v4f32(<4 x float> %x, <4 x float> %y) {
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; SIMD129-VM-NOT: f62x2
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: f64x2.add $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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; SIMD128: f64x2.add $push0=, $0, $1 # encoding: [0xfd,0x7b]{{$}}
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; SIMD128: return $pop0 #
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define <2 x double> @add_v2f64(<2 x double> %x, <2 x double> %y) {
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%a = fadd <2 x double> %x, %y
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ret <2 x double> %a
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@ -224,8 +224,8 @@ define <2 x double> @add_v2f64(<2 x double> %x, <2 x double> %y) {
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; SIMD129-VM-NOT: f62x2
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: f64x2.sub $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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; SIMD128: f64x2.sub $push0=, $0, $1 # encoding: [0xfd,0x7d]{{$}}
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; SIMD128: return $pop0 #
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define <2 x double> @sub_v2f64(<2 x double> %x, <2 x double> %y) {
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%a = fsub <2 x double> %x, %y
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ret <2 x double> %a
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@ -236,8 +236,8 @@ define <2 x double> @sub_v2f64(<2 x double> %x, <2 x double> %y) {
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; SIMD129-VM-NOT: f62x2
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: f64x2.div $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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; SIMD128: f64x2.div $push0=, $0, $1 # encoding: [0xfd,0x7f]{{$}}
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; SIMD128: return $pop0 #
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define <2 x double> @div_v2f64(<2 x double> %x, <2 x double> %y) {
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%a = fdiv <2 x double> %x, %y
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ret <2 x double> %a
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@ -248,8 +248,8 @@ define <2 x double> @div_v2f64(<2 x double> %x, <2 x double> %y) {
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; SIMD129-VM-NOT: f62x2
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: f64x2.mul $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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; SIMD128: f64x2.mul $push0=, $0, $1 # encoding: [0xfd,0x81]{{$}}
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; SIMD128: return $pop0 #
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define <2 x double> @mul_v2f64(<2 x double> %x, <2 x double> %y) {
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%a = fmul <2 x double> %x, %y
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ret <2 x double> %a
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@ -1,6 +1,6 @@
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,NO-SIMD128
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; RUN: llc < %s -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128
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; RUN: llc < %s -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128,+sign-ext --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128-VM
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; RUN: llc < %s -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-simd128,+sign-ext --show-mc-encoding | FileCheck %s --check-prefixes CHECK,NO-SIMD128
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; Test that basic SIMD128 vector manipulation operations assemble as expected.
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@ -10,36 +10,36 @@ target triple = "wasm32-unknown-unknown"
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; ==============================================================================
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; 16 x i8
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; ==============================================================================
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; CHECK-LABEL: extract_v16i8_s:{{$}}
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; CHECK-LABEL: extract_v16i8_s:
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; NO-SIMD128-NOT: i8x16
|
||||
; SIMD128: .param v128{{$}}
|
||||
; SIMD128: .result i32{{$}}
|
||||
; SIMD128: i8x16.extract_lane_s $push0=, $0, 13{{$}}
|
||||
; SIMD128: return $pop0{{$}}
|
||||
; SIMD128: i8x16.extract_lane_s $push0=, $0, 13 # encoding: [0xfd,0x09,0x0d]{{$}}
|
||||
; SIMD128: return $pop0 #
|
||||
define i32 @extract_v16i8_s(<16 x i8> %v) {
|
||||
%elem = extractelement <16 x i8> %v, i8 13
|
||||
%a = sext i8 %elem to i32
|
||||
ret i32 %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: extract_v16i8_u:{{$}}
|
||||
; CHECK-LABEL: extract_v16i8_u:
|
||||
; NO-SIMD128-NOT: i8x16
|
||||
; SIMD128: .param v128{{$}}
|
||||
; SIMD128: .result i32{{$}}
|
||||
; SIMD128: i8x16.extract_lane_u $push0=, $0, 13{{$}}
|
||||
; SIMD128: return $pop0{{$}}
|
||||
; SIMD128: i8x16.extract_lane_u $push0=, $0, 13 # encoding: [0xfd,0x0a,0x0d]{{$}}
|
||||
; SIMD128: return $pop0 #
|
||||
define i32 @extract_v16i8_u(<16 x i8> %v) {
|
||||
%elem = extractelement <16 x i8> %v, i8 13
|
||||
%a = zext i8 %elem to i32
|
||||
ret i32 %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: extract_v16i8:{{$}}
|
||||
; CHECK-LABEL: extract_v16i8:
|
||||
; NO-SIMD128-NOT: i8x16
|
||||
; SIMD128: .param v128{{$}}
|
||||
; SIMD128: .result i32{{$}}
|
||||
; SIMD128: i8x16.extract_lane_u $push0=, $0, 13{{$}}
|
||||
; SIMD128: return $pop0{{$}}
|
||||
; SIMD128: i8x16.extract_lane_u $push0=, $0, 13 # encoding: [0xfd,0x0a,0x0d]{{$}}
|
||||
; SIMD128: return $pop0 #
|
||||
define i8 @extract_v16i8(<16 x i8> %v) {
|
||||
%elem = extractelement <16 x i8> %v, i8 13
|
||||
ret i8 %elem
|
||||
|
|
@ -48,36 +48,36 @@ define i8 @extract_v16i8(<16 x i8> %v) {
|
|||
; ==============================================================================
|
||||
; 8 x i16
|
||||
; ==============================================================================
|
||||
; CHECK-LABEL: extract_v8i16_s:{{$}}
|
||||
; CHECK-LABEL: extract_v8i16_s:
|
||||
; NO-SIMD128-NOT: i16x8
|
||||
; SIMD128: .param v128{{$}}
|
||||
; SIMD128: .result i32{{$}}
|
||||
; SIMD128: i16x8.extract_lane_s $push0=, $0, 5{{$}}
|
||||
; SIMD128: return $pop0{{$}}
|
||||
; SIMD128: i16x8.extract_lane_s $push0=, $0, 5 # encoding: [0xfd,0x0b,0x05]{{$}}
|
||||
; SIMD128: return $pop0 #
|
||||
define i32 @extract_v8i16_s(<8 x i16> %v) {
|
||||
%elem = extractelement <8 x i16> %v, i16 5
|
||||
%a = sext i16 %elem to i32
|
||||
ret i32 %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: extract_v8i16_u:{{$}}
|
||||
; CHECK-LABEL: extract_v8i16_u:
|
||||
; NO-SIMD128-NOT: i16x8
|
||||
; SIMD128: .param v128{{$}}
|
||||
; SIMD128: .result i32{{$}}
|
||||
; SIMD128: i16x8.extract_lane_u $push0=, $0, 5{{$}}
|
||||
; SIMD128: return $pop0{{$}}
|
||||
; SIMD128: i16x8.extract_lane_u $push0=, $0, 5 # encoding: [0xfd,0x0c,0x05]{{$}}
|
||||
; SIMD128: return $pop0 #
|
||||
define i32 @extract_v8i16_u(<8 x i16> %v) {
|
||||
%elem = extractelement <8 x i16> %v, i16 5
|
||||
%a = zext i16 %elem to i32
|
||||
ret i32 %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: extract_v8i16:{{$}}
|
||||
; CHECK-LABEL: extract_v8i16:
|
||||
; NO-SIMD128-NOT: i16x8
|
||||
; SIMD128: .param v128{{$}}
|
||||
; SIMD128: .result i32{{$}}
|
||||
; SIMD128: i16x8.extract_lane_u $push0=, $0, 5{{$}}
|
||||
; SIMD128: return $pop0{{$}}
|
||||
; SIMD128: i16x8.extract_lane_u $push0=, $0, 5 # encoding: [0xfd,0x0c,0x05]{{$}}
|
||||
; SIMD128: return $pop0 #
|
||||
define i16 @extract_v8i16(<8 x i16> %v) {
|
||||
%elem = extractelement <8 x i16> %v, i16 5
|
||||
ret i16 %elem
|
||||
|
|
@ -86,12 +86,12 @@ define i16 @extract_v8i16(<8 x i16> %v) {
|
|||
; ==============================================================================
|
||||
; 4 x i32
|
||||
; ==============================================================================
|
||||
; CHECK-LABEL: extract_v4i32:{{$}}
|
||||
; CHECK-LABEL: extract_v4i32:
|
||||
; NO-SIMD128-NOT: i32x4
|
||||
; SIMD128: .param v128{{$}}
|
||||
; SIMD128: .result i32{{$}}
|
||||
; SIMD128: i32x4.extract_lane $push0=, $0, 3{{$}}
|
||||
; SIMD128: return $pop0{{$}}
|
||||
; SIMD128: i32x4.extract_lane $push0=, $0, 3 # encoding: [0xfd,0x0d,0x03]{{$}}
|
||||
; SIMD128: return $pop0 #
|
||||
define i32 @extract_v4i32(<4 x i32> %v) {
|
||||
%elem = extractelement <4 x i32> %v, i32 3
|
||||
ret i32 %elem
|
||||
|
|
@ -100,13 +100,13 @@ define i32 @extract_v4i32(<4 x i32> %v) {
|
|||
; ==============================================================================
|
||||
; 2 x i64
|
||||
; ==============================================================================
|
||||
; CHECK-LABEL: extract_v2i64:{{$}}
|
||||
; CHECK-LABEL: extract_v2i64:
|
||||
; NO-SIMD128-NOT: i64x2
|
||||
; SIMD128-VM-NOT: i64x2
|
||||
; SIMD128: .param v128{{$}}
|
||||
; SIMD128: .result i64{{$}}
|
||||
; SIMD128: i64x2.extract_lane $push0=, $0, 1{{$}}
|
||||
; SIMD128: return $pop0{{$}}
|
||||
; SIMD128: i64x2.extract_lane $push0=, $0, 1 # encoding: [0xfd,0x0e,0x01]{{$}}
|
||||
; SIMD128: return $pop0 #
|
||||
define i64 @extract_v2i64(<2 x i64> %v) {
|
||||
%elem = extractelement <2 x i64> %v, i64 1
|
||||
ret i64 %elem
|
||||
|
|
@ -115,12 +115,12 @@ define i64 @extract_v2i64(<2 x i64> %v) {
|
|||
; ==============================================================================
|
||||
; 4 x f32
|
||||
; ==============================================================================
|
||||
; CHECK-LABEL: extract_v4f32:{{$}}
|
||||
; CHECK-LABEL: extract_v4f32:
|
||||
; NO-SIMD128-NOT: f32x4
|
||||
; SIMD128: .param v128{{$}}
|
||||
; SIMD128: .result f32{{$}}
|
||||
; SIMD128: f32x4.extract_lane $push0=, $0, 3{{$}}
|
||||
; SIMD128: return $pop0{{$}}
|
||||
; SIMD128: f32x4.extract_lane $push0=, $0, 3 # encoding: [0xfd,0x0f,0x03]{{$}}
|
||||
; SIMD128: return $pop0 #
|
||||
define float @extract_v4f32(<4 x float> %v) {
|
||||
%elem = extractelement <4 x float> %v, i32 3
|
||||
ret float %elem
|
||||
|
|
@ -129,13 +129,13 @@ define float @extract_v4f32(<4 x float> %v) {
|
|||
; ==============================================================================
|
||||
; 2 x f64
|
||||
; ==============================================================================
|
||||
; CHECK-LABEL: extract_v2f64:{{$}}
|
||||
; CHECK-LABEL: extract_v2f64:
|
||||
; NO-SIMD128-NOT: f64x2
|
||||
; SIMD128-VM-NOT: f64x2
|
||||
; SIMD128: .param v128{{$}}
|
||||
; SIMD128: .result f64{{$}}
|
||||
; SIMD128: f64x2.extract_lane $push0=, $0, 1{{$}}
|
||||
; SIMD128: return $pop0{{$}}
|
||||
; SIMD128: f64x2.extract_lane $push0=, $0, 1 # encoding: [0xfd,0x10,0x01]{{$}}
|
||||
; SIMD128: return $pop0 #
|
||||
define double @extract_v2f64(<2 x double> %v) {
|
||||
%elem = extractelement <2 x double> %v, i32 1
|
||||
ret double %elem
|
||||
|
|
|
|||
Loading…
Reference in New Issue