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[x86] add tests for missed load folding; NFC 

llvm-svn: 345325
This commit is contained in:
Sanjay Patel 2018-10-25 22:23:27 +00:00
parent ea857e8225
commit c14aafdacc
2 changed files with 149 additions and 0 deletions
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92
llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
View File

@ -579,6 +579,98 @@ define <16 x i8> @shuffle_v16i8_16_17_18_19_04_05_06_07_24_25_10_11_28_13_30_15(
ret <16 x i8> %shuffle
}
; PR27780 - https://bugs.llvm.org/show_bug.cgi?id=27780
define <16 x i8> @load_fold_pblendvb(<16 x i8>* %px, <16 x i8> %y) {
; SSE2-LABEL: load_fold_pblendvb:
; SSE2: # %bb.0:
; SSE2-NEXT: movaps {{.*#+}} xmm1 = [255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255]
; SSE2-NEXT: andps %xmm1, %xmm0
; SSE2-NEXT: andnps (%rdi), %xmm1
; SSE2-NEXT: orps %xmm1, %xmm0
; SSE2-NEXT: retq
;
; SSSE3-LABEL: load_fold_pblendvb:
; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa (%rdi), %xmm1
; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1],zero,xmm0[3],zero,zero,zero,xmm0[7,8,9],zero,xmm0[11],zero,zero,zero,xmm0[15]
; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = zero,zero,xmm1[2],zero,xmm1[4,5,6],zero,zero,zero,xmm1[10],zero,xmm1[12,13,14],zero
; SSSE3-NEXT: por %xmm1, %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: load_fold_pblendvb:
; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: movdqa (%rdi), %xmm2
; SSE41-NEXT: movaps {{.*#+}} xmm0 = [255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255]
; SSE41-NEXT: pblendvb %xmm0, %xmm1, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: retq
;
; AVX1OR2-LABEL: load_fold_pblendvb:
; AVX1OR2: # %bb.0:
; AVX1OR2-NEXT: vmovdqa (%rdi), %xmm1
; AVX1OR2-NEXT: vmovdqa {{.*#+}} xmm2 = [255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255]
; AVX1OR2-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
; AVX1OR2-NEXT: retq
;
; AVX512VL-LABEL: load_fold_pblendvb:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: movw $29812, %ax # imm = 0x7474
; AVX512VL-NEXT: kmovd %eax, %k1
; AVX512VL-NEXT: vmovdqu8 (%rdi), %xmm0 {%k1}
; AVX512VL-NEXT: retq
%x = load <16 x i8>, <16 x i8>* %px, align 16
%select = shufflevector <16 x i8> %x, <16 x i8> %y, <16 x i32> <i32 16, i32 17, i32 2, i32 19, i32 4, i32 5, i32 6, i32 23, i32 24, i32 25, i32 10, i32 27, i32 12, i32 13, i32 14, i32 31>
ret <16 x i8> %select
}
define <16 x i8> @load_fold_pblendvb_commute(<16 x i8>* %px, <16 x i8> %y) {
; SSE2-LABEL: load_fold_pblendvb_commute:
; SSE2: # %bb.0:
; SSE2-NEXT: movaps {{.*#+}} xmm1 = [255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255]
; SSE2-NEXT: movaps %xmm1, %xmm2
; SSE2-NEXT: andnps %xmm0, %xmm2
; SSE2-NEXT: andps (%rdi), %xmm1
; SSE2-NEXT: orps %xmm2, %xmm1
; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: retq
;
; SSSE3-LABEL: load_fold_pblendvb_commute:
; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa (%rdi), %xmm1
; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = zero,zero,xmm0[2],zero,xmm0[4,5,6],zero,zero,zero,xmm0[10],zero,xmm0[12,13,14],zero
; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0,1],zero,xmm1[3],zero,zero,zero,xmm1[7,8,9],zero,xmm1[11],zero,zero,zero,xmm1[15]
; SSSE3-NEXT: por %xmm1, %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: load_fold_pblendvb_commute:
; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: movaps {{.*#+}} xmm0 = [255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255]
; SSE41-NEXT: pblendvb %xmm0, (%rdi), %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: retq
;
; AVX1OR2-LABEL: load_fold_pblendvb_commute:
; AVX1OR2: # %bb.0:
; AVX1OR2-NEXT: vmovdqa {{.*#+}} xmm1 = [255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255]
; AVX1OR2-NEXT: vpblendvb %xmm1, (%rdi), %xmm0, %xmm0
; AVX1OR2-NEXT: retq
;
; AVX512VL-LABEL: load_fold_pblendvb_commute:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa (%rdi), %xmm1
; AVX512VL-NEXT: movw $29812, %ax # imm = 0x7474
; AVX512VL-NEXT: kmovd %eax, %k1
; AVX512VL-NEXT: vmovdqu8 %xmm0, %xmm1 {%k1}
; AVX512VL-NEXT: vmovdqa %xmm1, %xmm0
; AVX512VL-NEXT: retq
%x = load <16 x i8>, <16 x i8>* %px, align 16
%select = shufflevector <16 x i8> %y, <16 x i8> %x, <16 x i32> <i32 16, i32 17, i32 2, i32 19, i32 4, i32 5, i32 6, i32 23, i32 24, i32 25, i32 10, i32 27, i32 12, i32 13, i32 14, i32 31>
ret <16 x i8> %select
}
define <16 x i8> @trunc_v4i32_shuffle(<16 x i8> %a) {
; SSE2-LABEL: trunc_v4i32_shuffle:
; SSE2: # %bb.0:

57
llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
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@ -1643,6 +1643,63 @@ define <32 x i8> @shuffle_v32i8_32_01_34_03_36_05_38_07_40_09_42_11_44_13_46_15_
ret <32 x i8> %shuffle
}
; PR27780 - https://bugs.llvm.org/show_bug.cgi?id=27780
define <32 x i8> @load_fold_pblendvb(<32 x i8>* %px, <32 x i8> %y) {
; AVX1-LABEL: load_fold_pblendvb:
; AVX1: # %bb.0:
; AVX1-NEXT: vbroadcastsd {{.*#+}} ymm1 = [-5.4861292804117373E+303,-5.4861292804117373E+303,-5.4861292804117373E+303,-5.4861292804117373E+303]
; AVX1-NEXT: vandnps (%rdi), %ymm1, %ymm2
; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: vorps %ymm2, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: load_fold_pblendvb:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovdqa (%rdi), %ymm1
; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255]
; AVX2-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0
; AVX2-NEXT: retq
;
; AVX512VL-LABEL: load_fold_pblendvb:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: movl $1953789044, %eax # imm = 0x74747474
; AVX512VL-NEXT: kmovd %eax, %k1
; AVX512VL-NEXT: vmovdqu8 (%rdi), %ymm0 {%k1}
; AVX512VL-NEXT: retq
%x = load <32 x i8>, <32 x i8>* %px, align 32
%select = shufflevector <32 x i8> %x, <32 x i8> %y, <32 x i32> <i32 32, i32 33, i32 2, i32 35, i32 4, i32 5, i32 6, i32 39, i32 40, i32 41, i32 10, i32 43, i32 12, i32 13, i32 14, i32 47, i32 48, i32 49, i32 18, i32 51, i32 20, i32 21, i32 22, i32 55, i32 56, i32 57, i32 26, i32 59, i32 28, i32 29, i32 30, i32 63>
ret <32 x i8> %select
}
define <32 x i8> @load_fold_pblendvb_commute(<32 x i8>* %px, <32 x i8> %y) {
; AVX1-LABEL: load_fold_pblendvb_commute:
; AVX1: # %bb.0:
; AVX1-NEXT: vbroadcastsd {{.*#+}} ymm1 = [-5.4861292804117373E+303,-5.4861292804117373E+303,-5.4861292804117373E+303,-5.4861292804117373E+303]
; AVX1-NEXT: vandnps %ymm0, %ymm1, %ymm0
; AVX1-NEXT: vandps (%rdi), %ymm1, %ymm1
; AVX1-NEXT: vorps %ymm0, %ymm1, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: load_fold_pblendvb_commute:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255]
; AVX2-NEXT: vpblendvb %ymm1, (%rdi), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512VL-LABEL: load_fold_pblendvb_commute:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa (%rdi), %ymm1
; AVX512VL-NEXT: movl $1953789044, %eax # imm = 0x74747474
; AVX512VL-NEXT: kmovd %eax, %k1
; AVX512VL-NEXT: vmovdqu8 %ymm0, %ymm1 {%k1}
; AVX512VL-NEXT: vmovdqa %ymm1, %ymm0
; AVX512VL-NEXT: retq
%x = load <32 x i8>, <32 x i8>* %px, align 32
%select = shufflevector <32 x i8> %y, <32 x i8> %x, <32 x i32> <i32 32, i32 33, i32 2, i32 35, i32 4, i32 5, i32 6, i32 39, i32 40, i32 41, i32 10, i32 43, i32 12, i32 13, i32 14, i32 47, i32 48, i32 49, i32 18, i32 51, i32 20, i32 21, i32 22, i32 55, i32 56, i32 57, i32 26, i32 59, i32 28, i32 29, i32 30, i32 63>
ret <32 x i8> %select
}
define <32 x i8> @shuffle_v32i8_zz_01_zz_03_zz_05_zz_07_zz_09_zz_11_zz_13_zz_15_zz_17_zz_19_zz_21_zz_23_zz_25_zz_27_zz_29_zz_31(<32 x i8> %a) {
; AVX1OR2-LABEL: shuffle_v32i8_zz_01_zz_03_zz_05_zz_07_zz_09_zz_11_zz_13_zz_15_zz_17_zz_19_zz_21_zz_23_zz_25_zz_27_zz_29_zz_31:
; AVX1OR2: # %bb.0: