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ARM assembly parsing for LSR/LSL/ROR(immediate). 

More of rdar://9704684

llvm-svn: 144301
This commit is contained in:
Jim Grosbach 2011-11-10 19:18:01 +00:00
parent 166c804893
commit c14871cc67
4 changed files with 83 additions and 12 deletions
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19
llvm/lib/Target/ARM/ARMInstrInfo.td
View File

@ -544,6 +544,14 @@ def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
let ParserMatchClass = Imm0_31AsmOperand;
}
/// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
def Imm0_32AsmOperand: AsmOperandClass { let Name = "Imm0_32"; }
def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
return Imm >= 0 && Imm < 32;
}]> {
let ParserMatchClass = Imm0_32AsmOperand;
}
/// imm0_255 predicate - Immediate in the range [0,255].
def Imm0_255AsmOperand : AsmOperandClass { let Name = "Imm0_255"; }
def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
@ -5001,5 +5009,14 @@ def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
// encoding. It seems we should be able to do that sort of thing
// in tblgen, but it could get ugly.
def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
(ins GPR:$Rd, GPR:$Rm, imm1_32:$imm, pred:$p,
(ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
cc_out:$s)>;
def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
(ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
cc_out:$s)>;
def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
(ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
cc_out:$s)>;
def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
(ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
cc_out:$s)>;

37
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -602,6 +602,14 @@ public:
int64_t Value = CE->getValue();
return Value > 0 && Value < 33;
}
bool isImm0_32() const {
if (Kind != k_Immediate)
return false;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (!CE) return false;
int64_t Value = CE->getValue();
return Value >= 0 && Value < 33;
}
bool isImm0_65535() const {
if (Kind != k_Immediate)
return false;
@ -1217,6 +1225,11 @@ public:
Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
}
void addImm0_32Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
addExpr(Inst, getImm());
}
void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
addExpr(Inst, getImm());
@ -4542,14 +4555,28 @@ processInstruction(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
switch (Inst.getOpcode()) {
// Handle the MOV complex aliases.
case ARM::ASRi: {
unsigned Amt = Inst.getOperand(2).getImm() + 1;
unsigned ShiftOp = ARM_AM::getSORegOpc(ARM_AM::asr, Amt);
case ARM::ASRi:
case ARM::LSRi:
case ARM::LSLi:
case ARM::RORi: {
ARM_AM::ShiftOpc ShiftTy;
unsigned Amt = Inst.getOperand(2).getImm();
switch(Inst.getOpcode()) {
default: llvm_unreachable("unexpected opcode!");
case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
case ARM::RORi: ShiftTy = ARM_AM::ror; break;
}
// A shift by zero is a plain MOVr, not a MOVsi.
unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
MCInst TmpInst;
TmpInst.setOpcode(ARM::MOVsi);
TmpInst.setOpcode(Opc);
TmpInst.addOperand(Inst.getOperand(0)); // Rd
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(MCOperand::CreateImm(ShiftOp)); // Shift value and ty
if (Opc == ARM::MOVsi)
TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
TmpInst.addOperand(Inst.getOperand(4));
TmpInst.addOperand(Inst.getOperand(5)); // cc_out

35
llvm/test/MC/ARM/basic-arm-instructions.s
View File

@ -261,9 +261,11 @@ Lforward:
@------------------------------------------------------------------------------
asr r2, r4, #32
asr r2, r4, #2
asr r2, r4, #0
@ CHECK: asr r2, r4, #32 @ encoding: [0x44,0x20,0xa0,0xe1]
@ CHECK: asr r2, r4, #2 @ encoding: [0x44,0x21,0xa0,0xe1]
@ CHECK: mov r2, r4 @ encoding: [0x04,0x20,0xa0,0xe1]
@------------------------------------------------------------------------------
@ -787,11 +789,28 @@ Lforward:
@ CHECK: ldrhthi r8, [r11], #0 @ encoding: [0xb0,0x80,0xfb,0x80]
@------------------------------------------------------------------------------
@ FIXME: LSL
@ LSL
@------------------------------------------------------------------------------
lsl r2, r4, #31
lsl r2, r4, #1
lsl r2, r4, #0
@ CHECK: lsl r2, r4, #31 @ encoding: [0x84,0x2f,0xa0,0xe1]
@ CHECK: lsl r2, r4, #1 @ encoding: [0x84,0x20,0xa0,0xe1]
@ CHECK: mov r2, r4 @ encoding: [0x04,0x20,0xa0,0xe1]
@------------------------------------------------------------------------------
@ FIXME: LSR
@ LSR
@------------------------------------------------------------------------------
lsr r2, r4, #32
lsr r2, r4, #2
lsr r2, r4, #0
@ CHECK: lsr r2, r4, #32 @ encoding: [0x24,0x20,0xa0,0xe1]
@ CHECK: lsr r2, r4, #2 @ encoding: [0x24,0x21,0xa0,0xe1]
@ CHECK: mov r2, r4 @ encoding: [0x04,0x20,0xa0,0xe1]
@------------------------------------------------------------------------------
@ MCR/MCR2
@ -1319,6 +1338,18 @@ Lforward:
@ CHECK: rfeia r1! @ encoding: [0x00,0x0a,0xb1,0xf8]
@------------------------------------------------------------------------------
@ ROR
@------------------------------------------------------------------------------
ror r2, r4, #31
ror r2, r4, #1
ror r2, r4, #0
@ CHECK: ror r2, r4, #31 @ encoding: [0xe4,0x2f,0xa0,0xe1]
@ CHECK: ror r2, r4, #1 @ encoding: [0xe4,0x20,0xa0,0xe1]
@ CHECK: mov r2, r4 @ encoding: [0x04,0x20,0xa0,0xe1]
@------------------------------------------------------------------------------
@ RSB
@------------------------------------------------------------------------------

4
llvm/test/MC/ARM/thumb-diagnostics.s
View File

@ -24,13 +24,9 @@
@ Out of range immediates for ASR instruction.
asrs r2, r3, #33
asrs r2, r3, #0
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: asrs r2, r3, #33
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: asrs r2, r3, #0
@ CHECK-ERRORS: ^
@ Out of range immediates for BKPT instruction.
bkpt #256