forked from OSchip/llvm-project
Intel style asm variant does not need '%' prefix.
llvm-svn: 147453
This commit is contained in:
Devang Patel
parent
22d0974b40
commit
c1215324a3
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@ -225,22 +225,22 @@ class FPrST0PInst<bits<8> o, string asm>
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// of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
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// we have to put some 'r's in and take them out of weird places.
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def ADD_FST0r : FPST0rInst <0xC0, "fadd\t$op">;
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def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, %ST(0)}">;
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def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, ST(0)}">;
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def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp\t$op">;
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def SUBR_FST0r : FPST0rInst <0xE8, "fsubr\t$op">;
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def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, %ST(0)}">;
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def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, ST(0)}">;
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def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p\t$op">;
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def SUB_FST0r : FPST0rInst <0xE0, "fsub\t$op">;
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def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, %ST(0)}">;
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def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, ST(0)}">;
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def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p\t$op">;
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def MUL_FST0r : FPST0rInst <0xC8, "fmul\t$op">;
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def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, %ST(0)}">;
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def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, ST(0)}">;
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def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp\t$op">;
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def DIVR_FST0r : FPST0rInst <0xF8, "fdivr\t$op">;
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def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, %ST(0)}">;
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def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, ST(0)}">;
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def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p\t$op">;
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def DIV_FST0r : FPST0rInst <0xF0, "fdiv\t$op">;
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def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, %ST(0)}">;
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def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, ST(0)}">;
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def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p\t$op">;
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def COM_FST0r : FPST0rInst <0xD0, "fcom\t$op">;
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@ -330,21 +330,21 @@ defm CMOVNP : FPCMov<X86_COND_NP>;
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let Predicates = [HasCMov] in {
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// These are not factored because there's no clean way to pass DA/DB.
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def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
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"fcmovb\t{$op, %st(0)|%ST(0), $op}">, DA;
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"fcmovb\t{$op, %st(0)|ST(0), $op}">, DA;
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def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
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"fcmovbe\t{$op, %st(0)|%ST(0), $op}">, DA;
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"fcmovbe\t{$op, %st(0)|ST(0), $op}">, DA;
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def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
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"fcmove\t{$op, %st(0)|%ST(0), $op}">, DA;
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"fcmove\t{$op, %st(0)|ST(0), $op}">, DA;
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def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
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"fcmovu\t {$op, %st(0)|%ST(0), $op}">, DA;
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"fcmovu\t {$op, %st(0)|ST(0), $op}">, DA;
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def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
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"fcmovnb\t{$op, %st(0)|%ST(0), $op}">, DB;
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"fcmovnb\t{$op, %st(0)|ST(0), $op}">, DB;
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def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
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"fcmovnbe\t{$op, %st(0)|%ST(0), $op}">, DB;
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"fcmovnbe\t{$op, %st(0)|ST(0), $op}">, DB;
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def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
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"fcmovne\t{$op, %st(0)|%ST(0), $op}">, DB;
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"fcmovne\t{$op, %st(0)|ST(0), $op}">, DB;
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def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
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"fcmovnu\t{$op, %st(0)|%ST(0), $op}">, DB;
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"fcmovnu\t{$op, %st(0)|ST(0), $op}">, DB;
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} // Predicates = [HasCMov]
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// Floating point loads & stores.
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@ -27,7 +27,7 @@ def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
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"shl{l}\t{%cl, $dst|$dst, CL}",
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[(set GR32:$dst, (shl GR32:$src1, CL))]>;
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def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
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"shl{q}\t{%cl, $dst|$dst, %CL}",
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"shl{q}\t{%cl, $dst|$dst, CL}",
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[(set GR64:$dst, (shl GR64:$src1, CL))]>;
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} // Uses = [CL]
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@ -74,7 +74,7 @@ def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
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"shl{l}\t{%cl, $dst|$dst, CL}",
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[(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
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def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
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"shl{q}\t{%cl, $dst|$dst, %CL}",
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"shl{q}\t{%cl, $dst|$dst, CL}",
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[(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
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}
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def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
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@ -118,7 +118,7 @@ def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
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"shr{l}\t{%cl, $dst|$dst, CL}",
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[(set GR32:$dst, (srl GR32:$src1, CL))]>;
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def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
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"shr{q}\t{%cl, $dst|$dst, %CL}",
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"shr{q}\t{%cl, $dst|$dst, CL}",
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[(set GR64:$dst, (srl GR64:$src1, CL))]>;
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}
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@ -163,7 +163,7 @@ def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
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"shr{l}\t{%cl, $dst|$dst, CL}",
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[(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
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def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
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"shr{q}\t{%cl, $dst|$dst, %CL}",
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"shr{q}\t{%cl, $dst|$dst, CL}",
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[(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
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}
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def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
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@ -206,7 +206,7 @@ def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
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"sar{l}\t{%cl, $dst|$dst, CL}",
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[(set GR32:$dst, (sra GR32:$src1, CL))]>;
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def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
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"sar{q}\t{%cl, $dst|$dst, %CL}",
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"sar{q}\t{%cl, $dst|$dst, CL}",
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[(set GR64:$dst, (sra GR64:$src1, CL))]>;
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}
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@ -252,7 +252,7 @@ def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
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"sar{l}\t{%cl, $dst|$dst, CL}",
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[(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
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def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
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"sar{q}\t{%cl, $dst|$dst, %CL}",
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"sar{q}\t{%cl, $dst|$dst, CL}",
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[(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
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}
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def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
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@ -424,7 +424,7 @@ def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
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"rol{l}\t{%cl, $dst|$dst, CL}",
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[(set GR32:$dst, (rotl GR32:$src1, CL))]>;
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def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
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"rol{q}\t{%cl, $dst|$dst, %CL}",
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"rol{q}\t{%cl, $dst|$dst, CL}",
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[(set GR64:$dst, (rotl GR64:$src1, CL))]>;
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}
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@ -469,7 +469,7 @@ def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
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"rol{l}\t{%cl, $dst|$dst, CL}",
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[(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
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def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
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"rol{q}\t{%cl, $dst|$dst, %CL}",
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"rol{q}\t{%cl, $dst|$dst, %cl}",
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[(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
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}
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def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src1),
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@ -513,7 +513,7 @@ def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
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"ror{l}\t{%cl, $dst|$dst, CL}",
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[(set GR32:$dst, (rotr GR32:$src1, CL))]>;
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def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
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"ror{q}\t{%cl, $dst|$dst, %CL}",
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"ror{q}\t{%cl, $dst|$dst, CL}",
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[(set GR64:$dst, (rotr GR64:$src1, CL))]>;
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}
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@ -558,7 +558,7 @@ def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
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"ror{l}\t{%cl, $dst|$dst, CL}",
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[(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
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def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
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"ror{q}\t{%cl, $dst|$dst, %CL}",
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"ror{q}\t{%cl, $dst|$dst, CL}",
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[(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
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}
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def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
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@ -618,12 +618,12 @@ def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
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[(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
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def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
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(ins GR64:$src1, GR64:$src2),
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"shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
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"shld{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
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[(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>,
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TB;
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def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
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(ins GR64:$src1, GR64:$src2),
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"shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
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"shrd{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
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[(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>,
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TB;
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}
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@ -694,11 +694,11 @@ def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
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addr:$dst)]>, TB;
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def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
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"shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
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"shld{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
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[(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
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addr:$dst)]>, TB;
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def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
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"shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
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"shrd{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
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[(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
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addr:$dst)]>, TB;
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}
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