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[X86] Strip unnecessary x87 instruction instrw overrides from scheduler models. 

llvm-svn: 330501
This commit is contained in:
Simon Pilgrim 2018-04-21 11:25:02 +00:00
parent 592d29a3b9
commit c0f654f18e
3 changed files with 4 additions and 52 deletions
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14
llvm/lib/Target/X86/X86SchedBroadwell.td
View File

@ -765,20 +765,11 @@ def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup27], (instregex "ADD_FPrST0",
"ADD_FST0r",
"ADD_FrST0",
"MMX_CVTPI2PSirr",
def: InstRW<[BWWriteResGroup27], (instregex "MMX_CVTPI2PSirr",
"PDEP(32|64)rr",
"PEXT(32|64)rr",
"SHLD(16|32|64)rri8",
"SHRD(16|32|64)rri8",
"SUBR_FPrST0",
"SUBR_FST0r",
"SUBR_FrST0",
"SUB_FPrST0",
"SUB_FST0r",
"SUB_FrST0",
"(V?)CVTDQ2PS(Y?)rr",
"(V?)CVTPS2DQ(Y?)rr",
"(V?)CVTTPS2DQ(Y?)rr")>;
@ -1028,9 +1019,6 @@ def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMADDUBSWrr",
"MMX_PMULHWirr",
"MMX_PMULLWirr",
"MMX_PMULUDQirr",
"MUL_FPrST0",
"MUL_FST0r",
"MUL_FrST0",
"(V?)PCMPGTQ(Y?)rr",
"(V?)PHMINPOSUWrr",
"(V?)PMADDUBSW(Y?)rr",

14
llvm/lib/Target/X86/X86SchedHaswell.td
View File

@ -1643,20 +1643,11 @@ def HWWriteResGroup50 : SchedWriteRes<[HWPort1]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[HWWriteResGroup50], (instregex "ADD_FPrST0",
"ADD_FST0r",
"ADD_FrST0",
"MMX_CVTPI2PSirr",
def: InstRW<[HWWriteResGroup50], (instregex "MMX_CVTPI2PSirr",
"PDEP(32|64)rr",
"PEXT(32|64)rr",
"SHLD(16|32|64)rri8",
"SHRD(16|32|64)rri8",
"SUBR_FPrST0",
"SUBR_FST0r",
"SUBR_FrST0",
"SUB_FPrST0",
"SUB_FST0r",
"SUB_FrST0",
"(V?)ADDPD(Y?)rr",
"(V?)ADDPS(Y?)rr",
"(V?)ADDSDrr",
@ -2189,9 +2180,6 @@ def: InstRW<[HWWriteResGroup89], (instregex "MMX_PMADDUBSWrr",
"MMX_PMULHWirr",
"MMX_PMULLWirr",
"MMX_PMULUDQirr",
"MUL_FPrST0",
"MUL_FST0r",
"MUL_FrST0",
"(V?)PCMPGTQ(Y?)rr",
"(V?)PHMINPOSUWrr",
"(V?)PMADDUBSW(Y?)rr",

28
llvm/lib/Target/X86/X86SchedSandyBridge.td
View File

@ -587,17 +587,8 @@ def SBWriteResGroup21 : SchedWriteRes<[SBPort1]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup21], (instregex "ADD_FPrST0",
"ADD_FST0r",
"ADD_FrST0",
"MMX_CVTPI2PSirr",
def: InstRW<[SBWriteResGroup21], (instregex "MMX_CVTPI2PSirr",
"PUSHFS64",
"SUBR_FPrST0",
"SUBR_FST0r",
"SUBR_FrST0",
"SUB_FPrST0",
"SUB_FST0r",
"SUB_FrST0",
"(V?)CVTDQ2PS(Y?)rr",
"(V?)CVTPS2DQ(Y?)rr",
"(V?)CVTTPS2DQ(Y?)rr")>;
@ -761,10 +752,7 @@ def SBWriteResGroup30 : SchedWriteRes<[SBPort0]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup30], (instregex "MUL_FPrST0",
"MUL_FST0r",
"MUL_FrST0",
"(V?)PCMPGTQrr")>;
def: InstRW<[SBWriteResGroup30], (instregex "(V?)PCMPGTQrr")>;
def SBWriteResGroup31 : SchedWriteRes<[SBPort23]> {
let Latency = 5;
@ -1807,18 +1795,6 @@ def SBWriteResGroup126 : SchedWriteRes<[SBPort0,SBFPDivider]> {
def: InstRW<[SBWriteResGroup126], (instregex "(V?)DIVPDrr",
"(V?)DIVSDrr")>;
def SBWriteResGroup127 : SchedWriteRes<[SBPort0]> {
let Latency = 24;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup127], (instregex "DIVR_FPrST0",
"DIVR_FST0r",
"DIVR_FrST0",
"DIV_FPrST0",
"DIV_FST0r",
"DIV_FrST0")>;
def SBWriteResGroup128 : SchedWriteRes<[SBPort0,SBPort23,SBFPDivider]> {
let Latency = 28;
let NumMicroOps = 2;