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AMDGPU/GlobalISel: InstrMapping for G_MERGE_VALUES 

llvm-svn: 327268
This commit is contained in:
Matt Arsenault 2018-03-12 13:35:49 +00:00
parent 503afda95f
commit c0aefd561e
3 changed files with 57 additions and 1 deletions
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12
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
View File

@ -317,6 +317,18 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
OpdsMapping[2] = nullptr;
break;
}
case AMDGPU::G_MERGE_VALUES: {
unsigned Bank = isSALUMapping(MI) ?
AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
unsigned SrcSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
OpdsMapping[0] = AMDGPU::getValueMapping(Bank, DstSize);
// Op1 and Dst should use the same register bank.
for (unsigned i = 1, e = MI.getNumOperands(); i != e; ++i)
OpdsMapping[i] = AMDGPU::getValueMapping(Bank, SrcSize);
break;
}
case AMDGPU::G_BITCAST: {
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);

2
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
View File

@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-- -O0 -run-pass=legalizer -global-isel %s | FileCheck %s
# RUN: llc -mtriple=amdgcn-- -O0 -run-pass=legalizer -global-isel -o - %s | FileCheck %s
---
name: test_merge_s32_s32_s64

44
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir Normal file
View File

@ -0,0 +1,44 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: merge_s32_s32_s64_s
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: merge_s32_s32_s64_s
; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
; CHECK: [[EXTRACT:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s64), 0
; CHECK: [[EXTRACT1:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s64), 32
; CHECK: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[EXTRACT]](s32), [[EXTRACT1]](s32)
; CHECK: S_ENDPGM implicit [[MV]](s64)
%0:_(s64) = COPY $sgpr0_sgpr1
%1:_(s32) = G_EXTRACT %0, 0
%2:_(s32) = G_EXTRACT %0, 32
%3:_(s64) = G_MERGE_VALUES %1, %2
S_ENDPGM implicit %3
...
---
name: merge_s32_s32_s64_v
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: merge_s32_s32_s64_v
; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
; CHECK: [[EXTRACT:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s64), 0
; CHECK: [[EXTRACT1:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s64), 32
; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[EXTRACT]](s32), [[EXTRACT1]](s32)
; CHECK: S_ENDPGM implicit [[MV]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_EXTRACT %0, 0
%2:_(s32) = G_EXTRACT %0, 32
%3:_(s64) = G_MERGE_VALUES %1, %2
S_ENDPGM implicit %3
...