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Encode the conditional execution predicate when JITing. 

llvm-svn: 57258
This commit is contained in:
Jim Grosbach 2008-10-07 19:05:35 +00:00
parent 422ef88f31
commit c084e84028
2 changed files with 16 additions and 10 deletions
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20
llvm/lib/Target/ARM/ARMCodeEmitter.cpp
View File

@ -256,8 +256,8 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
unsigned ARMCodeEmitter::getAddrModeNoneInstrBinary(const MachineInstr &MI, unsigned ARMCodeEmitter::getAddrModeNoneInstrBinary(const MachineInstr &MI,
const TargetInstrDesc &TID, const TargetInstrDesc &TID,
unsigned Binary) { unsigned Binary) {
// FIXME: Assume CC is AL for now. // Set the conditional execution predicate
Binary |= ARMCC::AL << 28; Binary |= II->getPredicate(&MI) << 28;
switch (TID.TSFlags & ARMII::FormMask) { switch (TID.TSFlags & ARMII::FormMask) {
default: default:
@ -376,8 +376,8 @@ void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI, unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
const TargetInstrDesc &TID, const TargetInstrDesc &TID,
unsigned Binary) { unsigned Binary) {
// FIXME: Assume CC is AL for now. // Set the conditional execution predicate
Binary |= ARMCC::AL << 28; Binary |= II->getPredicate(&MI) << 28;
// Encode S bit if MI modifies CPSR. // Encode S bit if MI modifies CPSR.
Binary |= getAddrMode1SBit(MI, TID); Binary |= getAddrMode1SBit(MI, TID);
@ -429,8 +429,8 @@ unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
unsigned ARMCodeEmitter::getAddrMode2InstrBinary(const MachineInstr &MI, unsigned ARMCodeEmitter::getAddrMode2InstrBinary(const MachineInstr &MI,
const TargetInstrDesc &TID, const TargetInstrDesc &TID,
unsigned Binary) { unsigned Binary) {
// FIXME: Assume CC is AL for now. // Set the conditional execution predicate
Binary |= ARMCC::AL << 28; Binary |= II->getPredicate(&MI) << 28;
// Set first operand // Set first operand
Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
@ -470,8 +470,8 @@ unsigned ARMCodeEmitter::getAddrMode2InstrBinary(const MachineInstr &MI,
unsigned ARMCodeEmitter::getAddrMode3InstrBinary(const MachineInstr &MI, unsigned ARMCodeEmitter::getAddrMode3InstrBinary(const MachineInstr &MI,
const TargetInstrDesc &TID, const TargetInstrDesc &TID,
unsigned Binary) { unsigned Binary) {
// FIXME: Assume CC is AL for now. // Set the conditional execution predicate
Binary |= ARMCC::AL << 28; Binary |= II->getPredicate(&MI) << 28;
// Set first operand // Set first operand
Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
@ -507,8 +507,8 @@ unsigned ARMCodeEmitter::getAddrMode3InstrBinary(const MachineInstr &MI,
unsigned ARMCodeEmitter::getAddrMode4InstrBinary(const MachineInstr &MI, unsigned ARMCodeEmitter::getAddrMode4InstrBinary(const MachineInstr &MI,
const TargetInstrDesc &TID, const TargetInstrDesc &TID,
unsigned Binary) { unsigned Binary) {
// FIXME: Assume CC is AL for now. // Set the conditional execution predicate
Binary |= ARMCC::AL << 28; Binary |= II->getPredicate(&MI) << 28;
// Set first operand // Set first operand
Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift; Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;

6
llvm/lib/Target/ARM/ARMInstrInfo.h
View File

@ -217,6 +217,12 @@ public:
// Predication support. // Predication support.
virtual bool isPredicated(const MachineInstr *MI) const; virtual bool isPredicated(const MachineInstr *MI) const;
ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
int PIdx = MI->findFirstPredOperandIdx();
return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
: ARMCC::AL;
}
virtual virtual
bool PredicateInstruction(MachineInstr *MI, bool PredicateInstruction(MachineInstr *MI,
const SmallVectorImpl<MachineOperand> &Pred) const; const SmallVectorImpl<MachineOperand> &Pred) const;