forked from OSchip/llvm-project
[MIPS GlobalISel] VarArg argument lowering, select G_VASTART and vacopy
CC_Mips doesn't accept vararg functions for O32, so we have to explicitly use CC_Mips_FixedArg. For lowerCall we now properly figure out whether callee function is vararg or not, this has no effect for O32 since we always use CC_Mips_FixedArg. For lower formal arguments we need to copy arguments in register to stack and save pointer to start for argument list into MipsMachineFunction object so that G_VASTART could use it during instruction select. For vacopy we need to copy content from one vreg to another, load and store are used for that purpose. Differential Revision: https://reviews.llvm.org/D67756 llvm-svn: 372555
This commit is contained in:
Petar Avramovic
parent
0e490ae0a9
commit
c063b0b0d3
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@ -454,10 +454,6 @@ bool MipsCallLowering::lowerFormalArguments(
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if (F.arg_empty())
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return true;
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if (F.isVarArg()) {
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return false;
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}
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for (auto &Arg : F.args()) {
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if (!isSupportedType(Arg.getType()))
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return false;
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@ -496,6 +492,40 @@ bool MipsCallLowering::lowerFormalArguments(
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if (!Handler.handle(ArgLocs, ArgInfos))
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return false;
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if (F.isVarArg()) {
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ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
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unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
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int VaArgOffset;
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unsigned RegSize = 4;
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if (ArgRegs.size() == Idx)
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VaArgOffset = alignTo(CCInfo.getNextStackOffset(), RegSize);
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else {
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VaArgOffset =
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(int)ABI.GetCalleeAllocdArgSizeInBytes(CCInfo.getCallingConv()) -
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(int)(RegSize * (ArgRegs.size() - Idx));
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}
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MachineFrameInfo &MFI = MF.getFrameInfo();
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int FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true);
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MF.getInfo<MipsFunctionInfo>()->setVarArgsFrameIndex(FI);
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for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) {
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MIRBuilder.getMBB().addLiveIn(ArgRegs[I]);
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MachineInstrBuilder Copy =
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MIRBuilder.buildCopy(LLT::scalar(RegSize * 8), Register(ArgRegs[I]));
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FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true);
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MachinePointerInfo MPO = MachinePointerInfo::getFixedStack(MF, FI);
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MachineInstrBuilder FrameIndex =
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MIRBuilder.buildFrameIndex(LLT::pointer(MPO.getAddrSpace(), 32), FI);
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, RegSize,
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/* Alignment */ RegSize);
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MIRBuilder.buildStore(Copy, FrameIndex, *MMO);
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}
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}
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return true;
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}
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@ -566,7 +596,12 @@ bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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subTargetRegTypeForCallingConv(F, ArgInfos, OrigArgIndices, Outs);
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SmallVector<CCValAssign, 8> ArgLocs;
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MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
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bool IsCalleeVarArg = false;
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if (Info.Callee.isGlobal()) {
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const Function *CF = static_cast<const Function *>(Info.Callee.getGlobal());
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IsCalleeVarArg = CF->isVarArg();
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}
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MipsCCState CCInfo(F.getCallingConv(), IsCalleeVarArg, MF, ArgLocs,
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F.getContext());
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CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(Info.CallConv), 1);
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@ -2869,7 +2869,7 @@ static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
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#include "MipsGenCallingConv.inc"
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CCAssignFn *MipsTargetLowering::CCAssignFnForCall() const{
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return CC_Mips;
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return CC_Mips_FixedArg;
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}
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CCAssignFn *MipsTargetLowering::CCAssignFnForReturn() const{
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@ -773,6 +773,29 @@ bool MipsInstructionSelector::select(MachineInstr &I) {
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MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SYNC)).addImm(0);
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break;
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}
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case G_VASTART: {
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MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
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int FI = FuncInfo->getVarArgsFrameIndex();
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Register LeaReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
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MachineInstr *LEA_ADDiu =
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BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LEA_ADDiu))
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.addDef(LeaReg)
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.addFrameIndex(FI)
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.addImm(0);
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if (!constrainSelectedInstRegOperands(*LEA_ADDiu, TII, TRI, RBI))
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return false;
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MachineInstr *Store = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SW))
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.addUse(LeaReg)
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.addUse(I.getOperand(0).getReg())
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.addImm(0);
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if (!constrainSelectedInstRegOperands(*Store, TII, TRI, RBI))
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return false;
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I.eraseFromParent();
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return true;
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}
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default:
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return false;
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}
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@ -122,6 +122,9 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
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getActionDefinitionsBuilder(G_DYN_STACKALLOC)
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.lowerFor({{p0, s32}});
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getActionDefinitionsBuilder(G_VASTART)
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.legalFor({p0});
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// FP instructions
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getActionDefinitionsBuilder(G_FCONSTANT)
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.legalFor({s32, s64});
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@ -252,6 +255,18 @@ bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
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MI.eraseFromParent();
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return constrainSelectedInstRegOperands(*Trap, TII, TRI, RBI);
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}
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case Intrinsic::vacopy: {
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Register Tmp = MRI.createGenericVirtualRegister(LLT::pointer(0, 32));
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MachinePointerInfo MPO;
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MIRBuilder.buildLoad(Tmp, MI.getOperand(2),
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*MI.getMF()->getMachineMemOperand(
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MPO, MachineMemOperand::MOLoad, 4, 4));
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MIRBuilder.buildStore(Tmp, MI.getOperand(1),
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*MI.getMF()->getMachineMemOperand(
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MPO, MachineMemOperand::MOStore, 4, 4));
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MI.eraseFromParent();
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return true;
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}
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default:
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break;
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}
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@ -403,6 +403,7 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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case G_SREM:
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case G_UREM:
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case G_BRINDIRECT:
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case G_VASTART:
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OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
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break;
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case G_LOAD: {
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@ -0,0 +1,127 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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--- |
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@.str = private unnamed_addr constant [11 x i8] c"string %s\0A\00", align 1
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declare void @llvm.va_start(i8*) #0
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declare void @llvm.va_copy(i8*, i8*) #0
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declare i32 @printf(i8*, ...)
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define void @testVaCopyArg(i8* %fmt, ...) {
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entry:
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%fmt.addr = alloca i8*, align 4
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%ap = alloca i8*, align 4
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%aq = alloca i8*, align 4
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%s = alloca i8*, align 4
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store i8* %fmt, i8** %fmt.addr, align 4
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%ap1 = bitcast i8** %ap to i8*
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call void @llvm.va_start(i8* %ap1)
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%0 = bitcast i8** %aq to i8*
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%1 = bitcast i8** %ap to i8*
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call void @llvm.va_copy(i8* %0, i8* %1)
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%argp.cur = load i8*, i8** %aq, align 4
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%argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4
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store i8* %argp.next, i8** %aq, align 4
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%2 = bitcast i8* %argp.cur to i8**
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%3 = load i8*, i8** %2, align 4
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store i8* %3, i8** %s, align 4
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%4 = load i8*, i8** %s, align 4
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%call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %4)
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ret void
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}
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...
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---
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name: testVaCopyArg
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$a0' }
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fixedStack:
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- { id: 0, offset: 12, size: 4, alignment: 4, isImmutable: true }
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- { id: 1, offset: 8, size: 4, alignment: 8, isImmutable: true }
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- { id: 2, offset: 4, size: 4, alignment: 4, isImmutable: true }
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- { id: 3, offset: 4, size: 4, alignment: 4, isImmutable: true }
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stack:
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- { id: 0, name: fmt.addr, size: 4, alignment: 4 }
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- { id: 1, name: ap, size: 4, alignment: 4 }
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- { id: 2, name: aq, size: 4, alignment: 4 }
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- { id: 3, name: s, size: 4, alignment: 4 }
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machineFunctionInfo: {}
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2, $a3
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; MIPS32-LABEL: name: testVaCopyArg
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; MIPS32: liveins: $a0, $a1, $a2, $a3
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.1, 0
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; MIPS32: SW [[COPY1]], [[ADDiu]], 0 :: (store 4 into %fixed-stack.1)
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; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
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; MIPS32: [[ADDiu1:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.2, 0
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; MIPS32: SW [[COPY2]], [[ADDiu1]], 0 :: (store 4 into %fixed-stack.2)
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; MIPS32: [[COPY3:%[0-9]+]]:gpr32 = COPY $a3
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; MIPS32: [[ADDiu2:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.3, 0
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; MIPS32: SW [[COPY3]], [[ADDiu2]], 0 :: (store 4 into %fixed-stack.3)
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; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @.str
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; MIPS32: [[ADDiu3:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @.str
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; MIPS32: [[ADDiu4:%[0-9]+]]:gpr32 = ADDiu %stack.0.fmt.addr, 0
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; MIPS32: [[ADDiu5:%[0-9]+]]:gpr32 = ADDiu %stack.1.ap, 0
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; MIPS32: [[ADDiu6:%[0-9]+]]:gpr32 = ADDiu %stack.2.aq, 0
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; MIPS32: [[ADDiu7:%[0-9]+]]:gpr32 = ADDiu %stack.3.s, 0
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; MIPS32: SW [[COPY]], [[ADDiu4]], 0 :: (store 4 into %ir.fmt.addr)
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; MIPS32: [[LEA_ADDiu:%[0-9]+]]:gpr32 = LEA_ADDiu %stack.0.fmt.addr, 0
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; MIPS32: SW [[LEA_ADDiu]], [[ADDiu5]], 0
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; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu5]], 0 :: (load 4)
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; MIPS32: SW [[LW]], [[ADDiu6]], 0 :: (store 4)
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; MIPS32: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDiu6]], 0 :: (load 4 from %ir.aq)
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; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 4
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; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[LW1]], [[ORi]]
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; MIPS32: SW [[ADDu]], [[ADDiu6]], 0 :: (store 4 into %ir.aq)
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; MIPS32: [[LW2:%[0-9]+]]:gpr32 = LW [[LW1]], 0 :: (load 4 from %ir.2)
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; MIPS32: SW [[LW2]], [[ADDiu7]], 0 :: (store 4 into %ir.s)
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; MIPS32: [[LW3:%[0-9]+]]:gpr32 = LW [[ADDiu7]], 0 :: (load 4 from %ir.s)
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; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
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; MIPS32: $a0 = COPY [[ADDiu3]]
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; MIPS32: $a1 = COPY [[LW3]]
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; MIPS32: JAL @printf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
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; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
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; MIPS32: RetRA
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%0:gprb(p0) = COPY $a0
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%1:gprb(s32) = COPY $a1
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%2:gprb(p0) = G_FRAME_INDEX %fixed-stack.2
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G_STORE %1(s32), %2(p0) :: (store 4 into %fixed-stack.2)
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%3:gprb(s32) = COPY $a2
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%4:gprb(p0) = G_FRAME_INDEX %fixed-stack.1
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G_STORE %3(s32), %4(p0) :: (store 4 into %fixed-stack.1)
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%5:gprb(s32) = COPY $a3
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%6:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
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G_STORE %5(s32), %6(p0) :: (store 4 into %fixed-stack.0)
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%18:gprb(p0) = G_GLOBAL_VALUE @.str
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%17:gprb(p0) = COPY %18(p0)
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%7:gprb(p0) = G_FRAME_INDEX %stack.0.fmt.addr
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%8:gpr32(p0) = G_FRAME_INDEX %stack.1.ap
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%9:gpr32(p0) = G_FRAME_INDEX %stack.2.aq
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%10:gprb(p0) = G_FRAME_INDEX %stack.3.s
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G_STORE %0(p0), %7(p0) :: (store 4 into %ir.fmt.addr)
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G_VASTART %8(p0) :: (store 4 into %ir.ap1, align 1)
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%19:gpr32 = LW %8(p0), 0 :: (load 4)
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SW %19, %9(p0), 0 :: (store 4)
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%11:gprb(p0) = G_LOAD %9(p0) :: (load 4 from %ir.aq)
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%12:gprb(s32) = G_CONSTANT i32 4
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%13:gprb(p0) = G_GEP %11, %12(s32)
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G_STORE %13(p0), %9(p0) :: (store 4 into %ir.aq)
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%14:gprb(p0) = G_LOAD %11(p0) :: (load 4 from %ir.2)
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G_STORE %14(p0), %10(p0) :: (store 4 into %ir.s)
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%15:gprb(p0) = G_LOAD %10(p0) :: (load 4 from %ir.s)
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ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
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$a0 = COPY %17(p0)
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$a1 = COPY %15(p0)
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JAL @printf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
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ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
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RetRA
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...
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@ -0,0 +1,66 @@
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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@.str = private unnamed_addr constant [11 x i8] c"string %s\0A\00", align 1
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declare void @llvm.va_start(i8*)
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declare void @llvm.va_copy(i8*, i8*)
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declare i32 @printf(i8*, ...)
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define void @testVaCopyArg(i8* %fmt, ...) {
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; MIPS32-LABEL: name: testVaCopyArg
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; MIPS32: bb.1.entry:
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; MIPS32: liveins: $a0, $a1, $a2, $a3
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; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
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; MIPS32: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store 4 into %fixed-stack.2)
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
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; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
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; MIPS32: G_STORE [[COPY2]](s32), [[FRAME_INDEX1]](p0) :: (store 4 into %fixed-stack.1)
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
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; MIPS32: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
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; MIPS32: G_STORE [[COPY3]](s32), [[FRAME_INDEX2]](p0) :: (store 4 into %fixed-stack.0)
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; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @.str
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; MIPS32: [[COPY4:%[0-9]+]]:_(p0) = COPY [[GV]](p0)
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; MIPS32: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.fmt.addr
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; MIPS32: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.ap
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; MIPS32: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.2.aq
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; MIPS32: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.3.s
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; MIPS32: G_STORE [[COPY]](p0), [[FRAME_INDEX3]](p0) :: (store 4 into %ir.fmt.addr)
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; MIPS32: G_VASTART [[FRAME_INDEX4]](p0) :: (store 4 into %ir.ap1, align 1)
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; MIPS32: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.va_copy), [[FRAME_INDEX5]](p0), [[FRAME_INDEX4]](p0)
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; MIPS32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX5]](p0) :: (load 4 from %ir.aq)
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; MIPS32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[LOAD]], [[C]](s32)
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; MIPS32: G_STORE [[GEP]](p0), [[FRAME_INDEX5]](p0) :: (store 4 into %ir.aq)
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; MIPS32: [[LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[LOAD]](p0) :: (load 4 from %ir.2)
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; MIPS32: G_STORE [[LOAD1]](p0), [[FRAME_INDEX6]](p0) :: (store 4 into %ir.s)
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; MIPS32: [[LOAD2:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX6]](p0) :: (load 4 from %ir.s)
|
||||
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
|
||||
; MIPS32: $a0 = COPY [[COPY4]](p0)
|
||||
; MIPS32: $a1 = COPY [[LOAD2]](p0)
|
||||
; MIPS32: JAL @printf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
|
||||
; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $v0
|
||||
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
|
||||
; MIPS32: RetRA
|
||||
entry:
|
||||
%fmt.addr = alloca i8*, align 4
|
||||
%ap = alloca i8*, align 4
|
||||
%aq = alloca i8*, align 4
|
||||
%s = alloca i8*, align 4
|
||||
store i8* %fmt, i8** %fmt.addr, align 4
|
||||
%ap1 = bitcast i8** %ap to i8*
|
||||
call void @llvm.va_start(i8* %ap1)
|
||||
%0 = bitcast i8** %aq to i8*
|
||||
%1 = bitcast i8** %ap to i8*
|
||||
call void @llvm.va_copy(i8* %0, i8* %1)
|
||||
%argp.cur = load i8*, i8** %aq, align 4
|
||||
%argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4
|
||||
store i8* %argp.next, i8** %aq, align 4
|
||||
%2 = bitcast i8* %argp.cur to i8**
|
||||
%3 = load i8*, i8** %2, align 4
|
||||
store i8* %3, i8** %s, align 4
|
||||
%4 = load i8*, i8** %s, align 4
|
||||
%call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %4)
|
||||
ret void
|
||||
}
|
||||
|
|
@ -0,0 +1,123 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
|
||||
--- |
|
||||
|
||||
@.str = private unnamed_addr constant [11 x i8] c"string %s\0A\00", align 1
|
||||
declare void @llvm.va_start(i8*) #0
|
||||
declare void @llvm.va_copy(i8*, i8*) #0
|
||||
declare i32 @printf(i8*, ...)
|
||||
|
||||
define void @testVaCopyArg(i8* %fmt, ...) {
|
||||
entry:
|
||||
%fmt.addr = alloca i8*, align 4
|
||||
%ap = alloca i8*, align 4
|
||||
%aq = alloca i8*, align 4
|
||||
%s = alloca i8*, align 4
|
||||
store i8* %fmt, i8** %fmt.addr, align 4
|
||||
%ap1 = bitcast i8** %ap to i8*
|
||||
call void @llvm.va_start(i8* %ap1)
|
||||
%0 = bitcast i8** %aq to i8*
|
||||
%1 = bitcast i8** %ap to i8*
|
||||
call void @llvm.va_copy(i8* %0, i8* %1)
|
||||
%argp.cur = load i8*, i8** %aq, align 4
|
||||
%argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4
|
||||
store i8* %argp.next, i8** %aq, align 4
|
||||
%2 = bitcast i8* %argp.cur to i8**
|
||||
%3 = load i8*, i8** %2, align 4
|
||||
store i8* %3, i8** %s, align 4
|
||||
%4 = load i8*, i8** %s, align 4
|
||||
%call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %4)
|
||||
ret void
|
||||
}
|
||||
|
||||
...
|
||||
---
|
||||
name: testVaCopyArg
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
liveins:
|
||||
- { reg: '$a0' }
|
||||
fixedStack:
|
||||
- { id: 0, offset: 12, size: 4, alignment: 4, isImmutable: true }
|
||||
- { id: 1, offset: 8, size: 4, alignment: 8, isImmutable: true }
|
||||
- { id: 2, offset: 4, size: 4, alignment: 4, isImmutable: true }
|
||||
- { id: 3, offset: 4, size: 4, alignment: 4, isImmutable: true }
|
||||
stack:
|
||||
- { id: 0, name: fmt.addr, size: 4, alignment: 4 }
|
||||
- { id: 1, name: ap, size: 4, alignment: 4 }
|
||||
- { id: 2, name: aq, size: 4, alignment: 4 }
|
||||
- { id: 3, name: s, size: 4, alignment: 4 }
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2, $a3
|
||||
|
||||
; MIPS32-LABEL: name: testVaCopyArg
|
||||
; MIPS32: liveins: $a0, $a1, $a2, $a3
|
||||
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
|
||||
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
|
||||
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
|
||||
; MIPS32: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store 4 into %fixed-stack.1)
|
||||
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
|
||||
; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
|
||||
; MIPS32: G_STORE [[COPY2]](s32), [[FRAME_INDEX1]](p0) :: (store 4 into %fixed-stack.2)
|
||||
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
|
||||
; MIPS32: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
|
||||
; MIPS32: G_STORE [[COPY3]](s32), [[FRAME_INDEX2]](p0) :: (store 4 into %fixed-stack.3)
|
||||
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @.str
|
||||
; MIPS32: [[COPY4:%[0-9]+]]:_(p0) = COPY [[GV]](p0)
|
||||
; MIPS32: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.fmt.addr
|
||||
; MIPS32: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.ap
|
||||
; MIPS32: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.2.aq
|
||||
; MIPS32: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.3.s
|
||||
; MIPS32: G_STORE [[COPY]](p0), [[FRAME_INDEX3]](p0) :: (store 4 into %ir.fmt.addr)
|
||||
; MIPS32: G_VASTART [[FRAME_INDEX4]](p0) :: (store 4 into %ir.ap1, align 1)
|
||||
; MIPS32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX4]](p0) :: (load 4)
|
||||
; MIPS32: G_STORE [[LOAD]](p0), [[FRAME_INDEX5]](p0) :: (store 4)
|
||||
; MIPS32: [[LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX5]](p0) :: (load 4 from %ir.aq)
|
||||
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
|
||||
; MIPS32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[LOAD1]], [[C]](s32)
|
||||
; MIPS32: G_STORE [[GEP]](p0), [[FRAME_INDEX5]](p0) :: (store 4 into %ir.aq)
|
||||
; MIPS32: [[LOAD2:%[0-9]+]]:_(p0) = G_LOAD [[LOAD1]](p0) :: (load 4 from %ir.2)
|
||||
; MIPS32: G_STORE [[LOAD2]](p0), [[FRAME_INDEX6]](p0) :: (store 4 into %ir.s)
|
||||
; MIPS32: [[LOAD3:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX6]](p0) :: (load 4 from %ir.s)
|
||||
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
|
||||
; MIPS32: $a0 = COPY [[COPY4]](p0)
|
||||
; MIPS32: $a1 = COPY [[LOAD3]](p0)
|
||||
; MIPS32: JAL @printf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
|
||||
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
|
||||
; MIPS32: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(s32) = COPY $a1
|
||||
%2:_(p0) = G_FRAME_INDEX %fixed-stack.2
|
||||
G_STORE %1(s32), %2(p0) :: (store 4 into %fixed-stack.2)
|
||||
%3:_(s32) = COPY $a2
|
||||
%4:_(p0) = G_FRAME_INDEX %fixed-stack.1
|
||||
G_STORE %3(s32), %4(p0) :: (store 4 into %fixed-stack.1)
|
||||
%5:_(s32) = COPY $a3
|
||||
%6:_(p0) = G_FRAME_INDEX %fixed-stack.0
|
||||
G_STORE %5(s32), %6(p0) :: (store 4 into %fixed-stack.0)
|
||||
%18:_(p0) = G_GLOBAL_VALUE @.str
|
||||
%17:_(p0) = COPY %18(p0)
|
||||
%7:_(p0) = G_FRAME_INDEX %stack.0.fmt.addr
|
||||
%8:_(p0) = G_FRAME_INDEX %stack.1.ap
|
||||
%9:_(p0) = G_FRAME_INDEX %stack.2.aq
|
||||
%10:_(p0) = G_FRAME_INDEX %stack.3.s
|
||||
G_STORE %0(p0), %7(p0) :: (store 4 into %ir.fmt.addr)
|
||||
G_VASTART %8(p0) :: (store 4 into %ir.ap1, align 1)
|
||||
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.va_copy), %9(p0), %8(p0)
|
||||
%11:_(p0) = G_LOAD %9(p0) :: (load 4 from %ir.aq)
|
||||
%12:_(s32) = G_CONSTANT i32 4
|
||||
%13:_(p0) = G_GEP %11, %12(s32)
|
||||
G_STORE %13(p0), %9(p0) :: (store 4 into %ir.aq)
|
||||
%14:_(p0) = G_LOAD %11(p0) :: (load 4 from %ir.2)
|
||||
G_STORE %14(p0), %10(p0) :: (store 4 into %ir.s)
|
||||
%15:_(p0) = G_LOAD %10(p0) :: (load 4 from %ir.s)
|
||||
ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
|
||||
$a0 = COPY %17(p0)
|
||||
$a1 = COPY %15(p0)
|
||||
JAL @printf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
|
||||
ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
|
||||
RetRA
|
||||
|
||||
...
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
|
||||
|
||||
@.str = private unnamed_addr constant [11 x i8] c"string %s\0A\00", align 1
|
||||
declare void @llvm.va_start(i8*)
|
||||
declare void @llvm.va_copy(i8*, i8*)
|
||||
declare i32 @printf(i8*, ...)
|
||||
|
||||
define void @testVaCopyArg(i8* %fmt, ...) {
|
||||
; MIPS32-LABEL: testVaCopyArg:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: addiu $sp, $sp, -40
|
||||
; MIPS32-NEXT: .cfi_def_cfa_offset 40
|
||||
; MIPS32-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
|
||||
; MIPS32-NEXT: .cfi_offset 31, -4
|
||||
; MIPS32-NEXT: addiu $1, $sp, 44
|
||||
; MIPS32-NEXT: sw $5, 0($1)
|
||||
; MIPS32-NEXT: addiu $1, $sp, 48
|
||||
; MIPS32-NEXT: sw $6, 0($1)
|
||||
; MIPS32-NEXT: addiu $1, $sp, 52
|
||||
; MIPS32-NEXT: sw $7, 0($1)
|
||||
; MIPS32-NEXT: lui $1, %hi($.str)
|
||||
; MIPS32-NEXT: addiu $1, $1, %lo($.str)
|
||||
; MIPS32-NEXT: addiu $2, $sp, 32
|
||||
; MIPS32-NEXT: addiu $3, $sp, 28
|
||||
; MIPS32-NEXT: addiu $5, $sp, 24
|
||||
; MIPS32-NEXT: addiu $6, $sp, 20
|
||||
; MIPS32-NEXT: sw $4, 0($2)
|
||||
; MIPS32-NEXT: addiu $2, $sp, 44
|
||||
; MIPS32-NEXT: sw $2, 0($3)
|
||||
; MIPS32-NEXT: lw $2, 0($3)
|
||||
; MIPS32-NEXT: sw $2, 0($5)
|
||||
; MIPS32-NEXT: lw $2, 0($5)
|
||||
; MIPS32-NEXT: ori $3, $zero, 4
|
||||
; MIPS32-NEXT: addu $3, $2, $3
|
||||
; MIPS32-NEXT: sw $3, 0($5)
|
||||
; MIPS32-NEXT: lw $2, 0($2)
|
||||
; MIPS32-NEXT: sw $2, 0($6)
|
||||
; MIPS32-NEXT: lw $5, 0($6)
|
||||
; MIPS32-NEXT: move $4, $1
|
||||
; MIPS32-NEXT: jal printf
|
||||
; MIPS32-NEXT: nop
|
||||
; MIPS32-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload
|
||||
; MIPS32-NEXT: addiu $sp, $sp, 40
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%fmt.addr = alloca i8*, align 4
|
||||
%ap = alloca i8*, align 4
|
||||
%aq = alloca i8*, align 4
|
||||
%s = alloca i8*, align 4
|
||||
store i8* %fmt, i8** %fmt.addr, align 4
|
||||
%ap1 = bitcast i8** %ap to i8*
|
||||
call void @llvm.va_start(i8* %ap1)
|
||||
%0 = bitcast i8** %aq to i8*
|
||||
%1 = bitcast i8** %ap to i8*
|
||||
call void @llvm.va_copy(i8* %0, i8* %1)
|
||||
%argp.cur = load i8*, i8** %aq, align 4
|
||||
%argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4
|
||||
store i8* %argp.next, i8** %aq, align 4
|
||||
%2 = bitcast i8* %argp.cur to i8**
|
||||
%3 = load i8*, i8** %2, align 4
|
||||
store i8* %3, i8** %s, align 4
|
||||
%4 = load i8*, i8** %s, align 4
|
||||
%call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %4)
|
||||
ret void
|
||||
}
|
||||
|
|
@ -0,0 +1,125 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
|
||||
--- |
|
||||
|
||||
@.str = private unnamed_addr constant [11 x i8] c"string %s\0A\00", align 1
|
||||
declare void @llvm.va_start(i8*) #0
|
||||
declare void @llvm.va_copy(i8*, i8*) #0
|
||||
declare i32 @printf(i8*, ...)
|
||||
|
||||
define void @testVaCopyArg(i8* %fmt, ...) {
|
||||
entry:
|
||||
%fmt.addr = alloca i8*, align 4
|
||||
%ap = alloca i8*, align 4
|
||||
%aq = alloca i8*, align 4
|
||||
%s = alloca i8*, align 4
|
||||
store i8* %fmt, i8** %fmt.addr, align 4
|
||||
%ap1 = bitcast i8** %ap to i8*
|
||||
call void @llvm.va_start(i8* %ap1)
|
||||
%0 = bitcast i8** %aq to i8*
|
||||
%1 = bitcast i8** %ap to i8*
|
||||
call void @llvm.va_copy(i8* %0, i8* %1)
|
||||
%argp.cur = load i8*, i8** %aq, align 4
|
||||
%argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4
|
||||
store i8* %argp.next, i8** %aq, align 4
|
||||
%2 = bitcast i8* %argp.cur to i8**
|
||||
%3 = load i8*, i8** %2, align 4
|
||||
store i8* %3, i8** %s, align 4
|
||||
%4 = load i8*, i8** %s, align 4
|
||||
%call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %4)
|
||||
ret void
|
||||
}
|
||||
|
||||
...
|
||||
---
|
||||
name: testVaCopyArg
|
||||
alignment: 4
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
liveins:
|
||||
- { reg: '$a0' }
|
||||
fixedStack:
|
||||
- { id: 0, offset: 12, size: 4, alignment: 4, isImmutable: true }
|
||||
- { id: 1, offset: 8, size: 4, alignment: 8, isImmutable: true }
|
||||
- { id: 2, offset: 4, size: 4, alignment: 4, isImmutable: true }
|
||||
- { id: 3, offset: 4, size: 4, alignment: 4, isImmutable: true }
|
||||
stack:
|
||||
- { id: 0, name: fmt.addr, size: 4, alignment: 4 }
|
||||
- { id: 1, name: ap, size: 4, alignment: 4 }
|
||||
- { id: 2, name: aq, size: 4, alignment: 4 }
|
||||
- { id: 3, name: s, size: 4, alignment: 4 }
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2, $a3
|
||||
|
||||
; MIPS32-LABEL: name: testVaCopyArg
|
||||
; MIPS32: liveins: $a0, $a1, $a2, $a3
|
||||
; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
|
||||
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
|
||||
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.1
|
||||
; MIPS32: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store 4 into %fixed-stack.1)
|
||||
; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
|
||||
; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.2
|
||||
; MIPS32: G_STORE [[COPY2]](s32), [[FRAME_INDEX1]](p0) :: (store 4 into %fixed-stack.2)
|
||||
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY $a3
|
||||
; MIPS32: [[FRAME_INDEX2:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.3
|
||||
; MIPS32: G_STORE [[COPY3]](s32), [[FRAME_INDEX2]](p0) :: (store 4 into %fixed-stack.3)
|
||||
; MIPS32: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @.str
|
||||
; MIPS32: [[COPY4:%[0-9]+]]:gprb(p0) = COPY [[GV]](p0)
|
||||
; MIPS32: [[FRAME_INDEX3:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %stack.0.fmt.addr
|
||||
; MIPS32: [[FRAME_INDEX4:%[0-9]+]]:gpr32(p0) = G_FRAME_INDEX %stack.1.ap
|
||||
; MIPS32: [[FRAME_INDEX5:%[0-9]+]]:gpr32(p0) = G_FRAME_INDEX %stack.2.aq
|
||||
; MIPS32: [[FRAME_INDEX6:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %stack.3.s
|
||||
; MIPS32: G_STORE [[COPY]](p0), [[FRAME_INDEX3]](p0) :: (store 4 into %ir.fmt.addr)
|
||||
; MIPS32: G_VASTART [[FRAME_INDEX4]](p0) :: (store 4 into %ir.ap1, align 1)
|
||||
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[FRAME_INDEX4]](p0), 0 :: (load 4)
|
||||
; MIPS32: SW [[LW]], [[FRAME_INDEX5]](p0), 0 :: (store 4)
|
||||
; MIPS32: [[LOAD:%[0-9]+]]:gprb(p0) = G_LOAD [[FRAME_INDEX5]](p0) :: (load 4 from %ir.aq)
|
||||
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
|
||||
; MIPS32: [[GEP:%[0-9]+]]:gprb(p0) = G_GEP [[LOAD]], [[C]](s32)
|
||||
; MIPS32: G_STORE [[GEP]](p0), [[FRAME_INDEX5]](p0) :: (store 4 into %ir.aq)
|
||||
; MIPS32: [[LOAD1:%[0-9]+]]:gprb(p0) = G_LOAD [[LOAD]](p0) :: (load 4 from %ir.2)
|
||||
; MIPS32: G_STORE [[LOAD1]](p0), [[FRAME_INDEX6]](p0) :: (store 4 into %ir.s)
|
||||
; MIPS32: [[LOAD2:%[0-9]+]]:gprb(p0) = G_LOAD [[FRAME_INDEX6]](p0) :: (load 4 from %ir.s)
|
||||
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
|
||||
; MIPS32: $a0 = COPY [[COPY4]](p0)
|
||||
; MIPS32: $a1 = COPY [[LOAD2]](p0)
|
||||
; MIPS32: JAL @printf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
|
||||
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
|
||||
; MIPS32: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(s32) = COPY $a1
|
||||
%2:_(p0) = G_FRAME_INDEX %fixed-stack.2
|
||||
G_STORE %1(s32), %2(p0) :: (store 4 into %fixed-stack.2)
|
||||
%3:_(s32) = COPY $a2
|
||||
%4:_(p0) = G_FRAME_INDEX %fixed-stack.1
|
||||
G_STORE %3(s32), %4(p0) :: (store 4 into %fixed-stack.1)
|
||||
%5:_(s32) = COPY $a3
|
||||
%6:_(p0) = G_FRAME_INDEX %fixed-stack.0
|
||||
G_STORE %5(s32), %6(p0) :: (store 4 into %fixed-stack.0)
|
||||
%18:_(p0) = G_GLOBAL_VALUE @.str
|
||||
%17:_(p0) = COPY %18(p0)
|
||||
%7:_(p0) = G_FRAME_INDEX %stack.0.fmt.addr
|
||||
%8:gpr32(p0) = G_FRAME_INDEX %stack.1.ap
|
||||
%9:gpr32(p0) = G_FRAME_INDEX %stack.2.aq
|
||||
%10:_(p0) = G_FRAME_INDEX %stack.3.s
|
||||
G_STORE %0(p0), %7(p0) :: (store 4 into %ir.fmt.addr)
|
||||
G_VASTART %8(p0) :: (store 4 into %ir.ap1, align 1)
|
||||
%19:gpr32 = LW %8(p0), 0 :: (load 4)
|
||||
SW %19, %9(p0), 0 :: (store 4)
|
||||
%11:_(p0) = G_LOAD %9(p0) :: (load 4 from %ir.aq)
|
||||
%12:_(s32) = G_CONSTANT i32 4
|
||||
%13:_(p0) = G_GEP %11, %12(s32)
|
||||
G_STORE %13(p0), %9(p0) :: (store 4 into %ir.aq)
|
||||
%14:_(p0) = G_LOAD %11(p0) :: (load 4 from %ir.2)
|
||||
G_STORE %14(p0), %10(p0) :: (store 4 into %ir.s)
|
||||
%15:_(p0) = G_LOAD %10(p0) :: (load 4 from %ir.s)
|
||||
ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
|
||||
$a0 = COPY %17(p0)
|
||||
$a1 = COPY %15(p0)
|
||||
JAL @printf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
|
||||
ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
|
||||
RetRA
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue