forked from OSchip/llvm-project
[Hexagon] Add implicit uses even when untied explicit uses are present
An explicit untied use is not sufficient to maintain liveness of a register redefined in a predicated instruction. For example %1 = COPY %0 ... %1 = A2_paddif %2, %1, 1 could become $r1 = COPY $r0 ... $r1 = A2_paddif $p0, $r1, 1 and later $r1 = COPY $r0 ;; this is not really dead! ... $r1 = A2_paddif $p0, $r0, 1 llvm-svn: 336662
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@ -499,6 +499,9 @@ void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM,
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if (!Op.isReg() || !DefRegs.count(Op))
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continue;
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if (Op.isDef()) {
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// Tied defs will always have corresponding uses, so no extra
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// implicit uses are needed.
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if (!Op.isTied())
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ImpUses.insert({Op, i});
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} else {
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// This function can be called for the same register with different
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@ -506,6 +509,7 @@ void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM,
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// register, we can get here more than once. Avoid adding multiple
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// implicit uses (or adding an implicit use when an explicit one is
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// present).
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if (Op.isTied())
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ImpUses.erase(Op);
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}
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}
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@ -0,0 +1,24 @@
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# RUN: llc -march=hexagon -run-pass=expand-condsets %s -o - | FileCheck %s
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# Check that there is a tied implicit use despite having an explicit (but
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# untied) use:
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# CHECK: %[[R:[0-9]+]]:intregs = A2_paddif killed %{{[0-9]+}}, %[[R]], 1, implicit %[[R]](tied-def 0)
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name: f0
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.1
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liveins: $r0, $r1
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%0:intregs = COPY $r0
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%1:intregs = COPY $r1
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%2:intregs = COPY $r0
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%3:intregs = M2_mpyi %2, %1
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%4:intregs = A2_sub %0, %3
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%5:predregs = C2_cmpeqi %4, 0
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%6:intregs = A2_addi %2, 1
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%7:intregs = C2_mux %5, %2, %6
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bb.1:
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...
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