forked from OSchip/llvm-project
Tweak x86 INC/DEC generation to look for CopyToReg or SETCC. Radar 7866163.
llvm-svn: 102477
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4bd85e47bf
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c0458f1a40
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@ -5918,15 +5918,20 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
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unsigned NumOperands = 0;
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unsigned NumOperands = 0;
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switch (Op.getNode()->getOpcode()) {
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switch (Op.getNode()->getOpcode()) {
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case ISD::ADD:
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case ISD::ADD:
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// Due to an isel shortcoming, be conservative if this add is likely to
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// Due to an isel shortcoming, be conservative if this add is
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// be selected as part of a load-modify-store instruction. When the root
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// likely to be selected as part of a load-modify-store
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// node in a match is a store, isel doesn't know how to remap non-chain
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// instruction. When the root node in a match is a store, isel
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// non-flag uses of other nodes in the match, such as the ADD in this
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// doesn't know how to remap non-chain non-flag uses of other
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// case. This leads to the ADD being left around and reselected, with
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// nodes in the match, such as the ADD in this case. This leads
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// the result being two adds in the output.
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// to the ADD being left around and reselected, with the result
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// being two adds in the output. Alas, even if none our users
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// are stores, that doesn't prove we're O.K. Ergo, if we have
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// any parents that aren't CopyToReg or SETCC, eschew INC/DEC.
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// A better fix seems to require climbing the DAG back to the
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// root, and it doesn't seem to be worth the effort.
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for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
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for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
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UE = Op.getNode()->use_end(); UI != UE; ++UI)
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UE = Op.getNode()->use_end(); UI != UE; ++UI)
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if (UI->getOpcode() == ISD::STORE)
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if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
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goto default_case;
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goto default_case;
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if (ConstantSDNode *C =
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if (ConstantSDNode *C =
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dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
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dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
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